Abstract: Embodiments of an apparatus are disclosed for performing arithmetic operations on provided operands. The apparatus may include a fetch unit, and an arithmetic logic unit (ALU). The fetch unit may be configured to retrieve two operands responsive to receiving an instruction, wherein the operands include binary-coded decimal values. The ALU may be configured to scale a value of each of the operands, and then compress the scaled values of the operands. The compressed values of the operands may include fewer data bits than the corresponding scaled values. The ALU may be further configured to estimate a portion of a result of the operation dependent upon the compressed values of the operands.

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

Abstract: Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.

Abstract: Apparatus for leading an animal. The apparatus includes a belt sized for encircling a user's hips. The belt has a closure for selectively joining longitudinally spaced portions of the belt to hold the belt in position around the user's hips with an upper edge. The apparatus includes an anchor connected to the belt adjacent the upper edge. The anchor spans a predetermined longitudinal distance along the belt. The apparatus includes a connector slidably mounted on the anchor for connecting an animal lead to the belt such that an upper end of the lead is selectively positionable along the anchor for guiding the animal circumferentially relative to the user while restraining the animal.

Abstract: Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the first CSA may receive partial products from the multiplier tree and an aligned addition term from the aligner. The system may include a fused/unfused multiply add (FUMA) block which may receive the first partial product, the second partial product, and the aligned addition term, wherein the first partial product and the second partial product are not truncated. The FUMA block may perform an unfused multiply add operation or a fused multiply add operation using the first partial product, the second partial product, and the aligned addition term, e.g., depending on an opcode or mode bit.

Abstract: A pipelined circuit for performing a divide operation on small operand sizes. The circuit includes a plurality of stages connected together in a series to perform a subtractive divide algorithm based on iterative subtractions and shifts. Each stage computes two quotient bits and outputs a partial remainder value to the next stage in the series. The first and last stages utilize a radix-4 serial architecture with edge modifications to increase efficiency. The intermediate stages utilize a radix-4 parallel architecture. The divide architecture is pipelined such that input operands can be applied to the divider on each clock cycle.

Abstract: A processor including instruction support for implementing hash algorithms may issue, for execution, programmer-selectable hash instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include hash instructions defined within the ISA. In addition, the hash instructions may be executable by the cryptographic unit to implement a hash that is compliant with one or more respective hash algorithm specifications. In response to receiving a particular hash instruction defined within the ISA, the cryptographic unit may retrieve a set of input data blocks from a predetermined set of architectural registers of the processor, and generate a hash value of the set of input data blocks according to a hash algorithm that corresponds to the particular hash instruction.

Abstract: A processing unit, system, and method for performing a multiply operation in a multiply-add pipeline. To reduce the pipeline latency, the unrounded result of a multiply-add operation is bypassed to the inputs of the multiply-add pipeline for use in a subsequent operation. If it is determined that rounding is required for the prior operation, then the rounding will occur during the subsequent operation. During the subsequent operation, a Booth encoder not utilized by the multiply operation will output a rounding correction factor as a selection input to a Booth multiplexer not utilized by the multiply operation. When the Booth multiplexer receives the rounding correction factor, the Booth multiplexer will output a rounding correction value to a carry save adder (CSA) tree, and the CSA tree will generate the correct sum from the rounding correction value and the other partial products.

Abstract: Apparatus (90) is provided for use in a stomach of a subject. The apparatus includes a balloon (92), adapted for placement in the stomach, and an anchor (102), coupled to the balloon. The anchor is adapted to prevent the balloon from passing into a duodenum of the subject. The apparatus further includes an inflation tube (96), coupled to the balloon to permit inflation of the balloon, and is adapted to stretch from the stomach to a mouth of the subject to facilitate inflation of the balloon. Other embodiments are also described.

Abstract: A freezer that uses liquid cryogen as a refrigerant includes an inner vessel defining a storage chamber and an outer jacket generally surrounding the inner vessel so that an insulation space is defined there between. A heat exchanger is positioned in a top portion of the storage chamber and has an inlet in communication with a supply of the liquid cryogen refrigerant so that the liquid cryogen refrigerant selectively flows through the heat exchanger to cool the storage chamber while being vaporized. A purge line is in communication with the outlet of the heat exchanger and includes a purge outlet positioned over the exterior of the heat exchanger. A purge valve is positioned within the purge line so that the vaporized liquid cryogen from the heat exchanger is selectively directed to the exterior of the heat exchanger to reduce ice formation on the heat exchanger.

Abstract: Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.

Abstract: Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these two single-precision instructions, especially on a register renaming machine, may result in the appropriate values for the two portions of the source register being stored in different physical locations, which can complicate execution of an instruction stream. In response to detecting a potential dependency, one or more instructions may be inserted in an instruction stream to enable the appropriate values to be stored within one physical double precision register, eliminating an actual or potential evil twin dependency.

Abstract: A floating-point circuit may include a floating-point operand normalization circuit configured to receive input floating-point operands of a given floating-point divide operation, the operands comprising a dividend and a divisor, as well as a divide engine coupled to the normalization circuit. In response to determining that one or more of the input floating-point operands is a denormal number, the operand normalization circuit may be further configured to normalize the one or more of the input floating-point operands and output a normalized dividend and normalized divisor to the divide engine, and dependent upon respective numbers of leading zeros of the dividend and divisor prior to normalization, generate a value indicative of a maximum possible number of digits of a quotient (NDQ). The divide engine may be configured to iteratively generate NDQ digits of a floating-point quotient from the normalized dividend and the normalized divisor provided by the floating-point operand normalization circuit.

Abstract: A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M.

Abstract: Apparatus is provided for use in a stomach of a subject. The apparatus includes a gastric balloon and an anchor coupled to the gastric balloon. The anchor includes a flexible tube, which, when in a relaxed position, is shaped so as to define a portion that prevents the anchor from passing into a duodenum of the subject. The anchor also includes one or more shape-controlling elements coupled to the portion and configured to control a shape of the portion. Other embodiments are also described.

Abstract: Apparatus (90) is provided for use in a stomach of a subject. The apparatus includes a balloon (92), adapted for placement in the stomach, and all anchor (102), coupled to the balloon. The anchor is adapted to prevent the balloon from passing into a duodenum of the subject. The apparatus further includes an inflation tube (96), coupled to the balloon to permit inflation of the balloon, and is adapted to stretch from the stomach to a mouth of the subject to facilitate inflation of the balloon. Other embodiments are also described.

Abstract: Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these two single-precision instructions, especially on a register renaming machine, may result in the appropriate values for the two portions of the source register being stored in different physical locations, which can complicate execution of an instruction stream. In response to detecting a potential dependency, one or more instructions may be inserted in an instruction stream to enable the appropriate values to be stored within one physical double precision register, eliminating an actual or potential evil twin dependency.

Abstract: Apparatus for use in a gastrointestinal tract of a subject, the apparatus including a straightening rod (8), and a flexible tubular anchor (1) having a distal end (2) and an open proximal end (4), and sized to fit in the gastrointestinal tract. The anchor (1) comprises a material that has an elastic memory which biases the anchor (1) towards assuming a pre-selected bent configuration. The anchor (1) is shaped so as to define a central core (7) extending from the open proximal end (4) toward the distal end (2). The anchor (1) is configured to be straightened from the pre-selected bent configuration by insertion of the straightening rod (8) in the central core (7). The apparatus further includes a device (70) coupled to the anchor, selected from the list consisting of: a therapeutic device, and a transmitting device. Other embodiments are also described.

Abstract: Techniques and structures are described which allow the detection of certain dependency conditions, including evil twin conditions, during the execution of computer instructions. Information used to detect dependencies may be stored in a logical map table, which may include a content-addressable memory. The logical map table may maintain a logical register to physical register mapping, including entries dedicated to physical registers available as rename registers. In one embodiment, each entry in the logical map table includes a first value usable to indicate whether only a portion of the physical register is valid and whether the physical register includes the most recent update to the logical register being renamed. Use of this first value may allow precise detection of dependency conditions, including evil twin conditions, upon an instruction reading from at least two portions of a logical register having an entry in the logical map table whose first value is set.