Abstract: A body pad for application to the skin for treating an ailment. The pad includes a pad body, a recess in the pad body extending from the outer surface of the pad body toward the inner surface a distance which is less than an overall thickness of the body, and a thin, flexible wall at a bottom of the recess. The wall is adapted to deform outwardly into the recess to provide a cavity between the pad body and the skin for holding a volume of medication which has been pre-applied to the skin. Other pad features are disclosed.

Abstract: An apparatus and method for integer to floating-point format conversion. A processor may include an adder configured to perform addition of respective mantissas of two floating-point operands to produce a sum, where a smaller-exponent one of the floating-point operands has a respective exponent less than or equal to a respective exponent of a larger-exponent one of the floating-point operands. The processor may further include an alignment shifter coupled to the adder and configured, in a first mode of operation, to align the floating-point operands prior to the addition by shifting the respective mantissa of the smaller-exponent operand towards a least-significant bit position. The alignment shifter may be further configured, in a second mode of operation, to normalize an integer operand by shifting the integer operand towards a most-significant bit position. The second mode of operation may be active during execution of an instruction to convert the integer operand to floating-point format.

Abstract: Apparatus is provided for use in a stomach of a subject, including a gastric balloon and a hollow, flexible tube coupled at a distal end thereof to the gastric balloon. A proximal portion of the tube, when in a relaxed position, is shaped so as to prevent the balloon from passing into a duodenum of the subject. The apparatus also includes an inflation conduit disposed in part within the distal end of the tube, the inflation conduit exiting the tube at a site proximal to the gastric balloon. Other embodiments are also provided.

Abstract: Apparatus for use in a gastrointestinal tract of a subject, the apparatus including a straightening rod (8), and a flexible tubular anchor (1) having a distal end (2) and an open proximal end (4), and sized to fit in the gastrointestinal tract. The anchor (1) comprises a material that has an elastic memory which biases the anchor (1) towards assuming a pre-selected bent configuration. The anchor (1) is shaped so as to define a central core (7) extending from the open proximal end (4) toward the distal end (2). The anchor (1) is configured to be straightened from the pre-selected bent configuration by insertion of the straightening rod (8) in the central core (7). The apparatus further includes a device (70) coupled to the anchor, selected from the list consisting of: a therapeutic device, and a transmitting device. Other embodiments are also described.

Abstract: Apparatus (90) is provided for use in a stomach of a subject. The apparatus includes a balloon (92), adapted for placement in the stomach, and all anchor (102), coupled to the balloon. The anchor is adapted to prevent the balloon from passing into a duodenum of the subject. The apparatus further includes an inflation tube (96), coupled to the balloon to permit inflation of the balloon, and is adapted to stretch from the stomach to a mouth of the subject to facilitate inflation of the balloon. Other embodiments are also described.

Abstract: Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the first CSA may receive partial products from the multiplier tree and an aligned addition term from the aligner. The system may include a fused/unfused multiply add (FUMA) block which may receive the first partial product, the second partial product, and the aligned addition term, wherein the first partial product and the second partial product are not truncated. The FUMA block may perform an unfused multiply add operation or a fused multiply add operation using the first partial product, the second partial product, and the aligned addition term, e.g., depending on an opcode or mode bit.

Abstract: A system for holding one or more implements. The system includes a wall-mounted rail having a channel-track extending lengthwise of the rail, and an implement holder having a track-engaging element slidable in the channel-track to a selected position on the rail. Fastener holes are spaced at intervals along the bottom wall of the channel-track for receiving one or more rail fasteners to mount the rail. One implement holder comprises a jar assembly which includes a jar for storing items and a bracket mountable on the rail for holding the jar. Other implement holders may also be used, including an implement holder with a snap-lock fastener for releasable snap-fastening interconnection with the rail. A support places the holder at a different position relative to the rail. A wall mounted bracket may be used for supporting the holder.

Abstract: A method and device divides a dividend by a divisor, the dividend and the divisor both being integers. The method and device determine a maximum possible number of quotient digits (NDQ) based on a number of significant digits of the divisor and the dividend, normalizes the dividend and divisor, and calculates NDQ number of quotient digits from the normalized divisor and dividend.

Abstract: A method and apparatus for controlling power consumption in a multi-threaded processor. In one embodiment, the processor includes at least one logic unit for processing instructions. The logic unit includes a plurality of positions, wherein each of the plurality of positions corresponds to at least one instruction thread. Clock signals may be provided to the logic unit via a clock gating unit. The clock gating unit is configured to inhibit a clock signal from being provided to a corresponding one of the thread positions when no instruction thread is active for that position. The inhibiting of the clock signal for an inactive thread position may reduce power consumption by the processor.

Abstract: An apparatus and method to support pipelining of variable-latency instructions in a multithreaded processor. In one embodiment, a processor may include instruction fetch logic configured to issue a first and a second instruction from different ones of a plurality of threads during successive cycles. The processor may also include first and second execution units respectively configured to execute shorter-latency and longer-latency instructions and to respectively write shorter-latency or longer-latency instruction results to a result write port during a first or second writeback stage. The first writeback stage may occur a fewer number of cycles after instruction issue than the second writeback stage. The instruction fetch logic may be further configured to guarantee result write port access by the second execution unit during the second writeback stage by preventing the shorter-latency instruction from issuing during a cycle for which the first writeback stage collides with the second writeback stage.

Abstract: An apparatus and method for floating-point special case handling. In one embodiment, a processor may include a first execution unit configured to execute a longer-latency floating-point instruction, and a second execution unit configured to execute a shorter-latency floating-point instruction. In response to the longer-latency floating-point instruction being issued to the first execution unit, the second execution unit may be further configured to detect whether a result of the longer-latency floating-point instruction is determinable from one or more operands of the longer-latency floating-point instruction independently of the first execution unit executing the longer-latency floating-point instruction. In response to detecting that the result is determinable, the second execution unit may be further configured to flush the longer-latency floating-point instruction from the first execution unit and to determine the result.

Abstract: A unified data flow is provided that allows multiplication of SIMD and non-SIMD multiplies in one multiplier. The multiplies may be both integer and floating point operations. The multiplier is partitionable having a plurality of sub-trees. The multiplier is configured to be a single tree structure in response to a non-SIMD multiplication instruction and as a partitioned tree structure in response to a SIMD multiplication instruction. At least two multiplication operations can be performed in parallel in the partitioned tree structure in response to the SIMD multiplication instruction and a single multiplication operation is performed in the single tree structure in response to the non-SIMD multiplication instruction. Appropriate formatting of the input operands and selection of data from the tree structures is performed in accordance with the instruction.

Abstract: In general, this invention is directed to a rail and slider system having residential and commercial organizational applications. In one aspect, the system comprises at least one rail and a slider mounted on the rail for sliding movement along the rail. The rail and slider have teeth which releasably engage with one another for locking the slider at selected positions along the rail. A spring device on the slider urges the slider toward a locked position. The slider is manually movable against the urging of the spring device from its locked position to an unlocked position in which the teeth on the arms and the tracks are disengaged to permit sliding movement of the slider along the rail to a different selected position. Various items can be attached to the slider, e.g., a funnel-shaped holder and shelf bracket.

Abstract: An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction from another one of the plurality of threads. The processor may also include floating-point arithmetic logic configured to execute a floating-point instruction issued by the instruction fetch logic from a given one of the plurality of threads, and further configured to determine whether the floating-point instruction generates an exception, and may further include exception prediction logic configured to predict whether the floating-point instruction will generate the exception, where the prediction occurs before the floating-point arithmetic logic determines whether the floating-point instruction generates the exception.

Abstract: In one embodiment, a processor is configured to execute a window swap instruction. The processor comprises a register file (that comprises a plurality of registers) and first and second execution units coupled to the register file. A first pipeline associated with the first execution unit has a first number of pipeline stages, and a second pipeline associated with the second execution unit has a second number of pipeline stages. The first execution unit is configured to change the current register window from the first register window to the second register window in the register file in response to the instruction. The second execution unit is configured to perform an operation defined by the instruction and write the result to the register file. The second number of pipeline stages exceeds the first number, whereby the second register window is established in the register file prior to writing the result.

Abstract: Footwear including an insole formed for relieving pressure on a common digital nerve of a foot. The insole has heel, mid and forefoot sections. The forefoot section of the insole is formed with a pad having a neuroma pad section which underlies the third and fourth metatarsal heads of the foot, so that when a bottom of the foot is placed on the insole, the neuroma pad section applies an upward force to the bottom of the foot sufficient to spread the third and fourth metatarsal heads away from one another and thereby relieve pressure on the third common digital nerve to reduce the risk of neuroma. In other embodiments, the pad is formed as a separate pad for placement in footwear. An insole designed for use with thonged footwear is also disclosed.

Abstract: A method of enabling a single instruction stream multiple data stream operation and a double precision floating point operation within a single floating point execution unit which includes providing a floating point unit with a two way aligner and a two way normalizer, selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed, and selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.

Abstract: A system and method for measuring the size of a person's foot so that properly sized shoes can be selected. The measuring system has a support surface having a transparent window, and a fixture positioned over the transparent window for receiving a foot to be scanned. The measuring system also includes an imaging device for scanning the foot in the fixture through the window to produce an image of a bottom surface of the foot superimposed on foot measuring indicia. In one embodiment, the fixture is shaped like a shoe. The person can print the image and use the image to select a properly sized pair of shoes.

Abstract: Footwear comprising a sole for supporting a foot and an upper attached to the sole for covering the foot and adjoining ankle. The sole and upper define an interior of the footwear and is sized and shaped for receiving the foot and ankle. The upper has an outer shell that forms an exterior of the footwear and an inner lining that is adjacent the foot and ankle when they are received in the interior of the footwear. A compressible generally U-shaped pad is positioned between the shell and the lining of the upper. The pad has a bottom section and a pair spaced-apart side sections extending up from the bottom section. The pad is sized and positioned in the upper such that when the foot and ankle are received in the footwear, the bottom section of the pad is disposed immediately below a medial malleolus of the foot and the side sections of the pad extend up along opposite sides of the medial malleolus up to at least about the distal neck of the tibia.

Abstract: Footwear comprising a sole. The sole has a heel section for supporting a heel of the foot. The heel section has medial and lateral regions. At least a portion of the lateral region has a first compressive resilience for attenuating the shock of impact to the wearer during running and walking. Further, the sole has an arch section forward of the heel section for supporting an arch of the foot. The arch section also has medial and lateral regions. At least a portion of the lateral region of the arch section has the first compressive resilience and at least a portion of the medial region of the arch section has a second compressive resilience harder than the first compressive resilience for providing firm support for the foot during running and walking. In addition, the sole has a forefoot section forward of the arch section for supporting a ball of the foot including first, second, third, fourth and fifth metatarsal heads and associated metatarsal necks, proximal phalanges and metatarsal phalangeal joints.