Patents by Inventor Jeffrey S. Flynn
Jeffrey S. Flynn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8698286Abstract: The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).Type: GrantFiled: February 12, 2013Date of Patent: April 15, 2014Assignee: Cree, Inc.Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo
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Patent number: 8390101Abstract: The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).Type: GrantFiled: March 23, 2012Date of Patent: March 5, 2013Assignee: Cree, Inc.Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo
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Publication number: 20120181547Abstract: The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).Type: ApplicationFiled: March 23, 2012Publication date: July 19, 2012Applicant: CREE, INC.Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo
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Patent number: 8212259Abstract: A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 102 microns per hour.Type: GrantFiled: December 6, 2002Date of Patent: July 3, 2012Assignee: Cree, Inc.Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo, David M. Keogh, Xueping Xu, Barbara E. Landini
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Patent number: 8174089Abstract: The present invention relates to various switching device structures including Schottky diode, P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).Type: GrantFiled: August 6, 2010Date of Patent: May 8, 2012Assignee: Cree, Inc.Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo
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Patent number: 8043731Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 ?m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3 E6 cm?2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. Both upper and lower surfaces may be offcut. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.Type: GrantFiled: February 26, 2010Date of Patent: October 25, 2011Assignee: Cree, Inc.Inventors: Xueping Xu, Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes
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Patent number: 7919791Abstract: A Group III-V nitride microelectronic device structure including a delta doped layer and/or a doped superlattice. A delta doping method is described, including the steps of: depositing semiconductor material on a substrate by a first epitaxial film growth process; terminating the deposition of semiconductor material on the substrate to present an epitaxial film surface; delta doping the semiconductor material at the epitaxial film surface, to form a delta doping layer thereon; terminating the delta doping; resuming deposition of semiconductor material to deposit semiconductor material on the delta doping layer, in a second epitaxial film growth process; and continuing the semiconductor material second epitaxial film growth process to a predetermined extent, to form a doped microelectronic device structure, wherein the delta doping layer is internalized in semiconductor material deposited in the first and second epitaxial film growth processes.Type: GrantFiled: March 25, 2002Date of Patent: April 5, 2011Assignee: Cree, Inc.Inventors: Jeffrey S. Flynn, George R. Brandes
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Patent number: 7915152Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.Type: GrantFiled: February 2, 2010Date of Patent: March 29, 2011Assignee: Cree, Inc.Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
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Publication number: 20100301351Abstract: The present invention relates to various switching device structures including Schottky diode, P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).Type: ApplicationFiled: August 6, 2010Publication date: December 2, 2010Applicant: CREE, INC.Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo
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Publication number: 20100289122Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.Type: ApplicationFiled: February 2, 2010Publication date: November 18, 2010Applicant: CREE, INC.Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
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Patent number: 7795707Abstract: The present invention relates to various switching device structures including Schottky diode (10), P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers (16) of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer (14). The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).Type: GrantFiled: April 30, 2003Date of Patent: September 14, 2010Assignee: Cree, Inc.Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo
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Publication number: 20100148320Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 ?m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm?2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. Both upper and lower surfaces may be offcut. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.Type: ApplicationFiled: February 26, 2010Publication date: June 17, 2010Applicant: CREE, INC.Inventors: Xueping Xu, Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes
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Patent number: 7700203Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 ?m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm?2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.Type: GrantFiled: April 14, 2008Date of Patent: April 20, 2010Assignee: Cree, Inc.Inventors: Xueping Xu, Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes
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Patent number: 7655197Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour.Type: GrantFiled: February 19, 2003Date of Patent: February 2, 2010Assignee: Cree, Inc.Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
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Publication number: 20080199649Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 ?m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm?2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.Type: ApplicationFiled: April 14, 2008Publication date: August 21, 2008Applicant: CREE, INC.Inventors: Xueping Xu, Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes
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Patent number: 7390581Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 ?m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm?2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.Type: GrantFiled: May 11, 2006Date of Patent: June 24, 2008Assignee: Cree, Inc.Inventors: Xueping Xu, Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes
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Patent number: 7282744Abstract: A III-nitride electronic device structure including doped material, an active region and a barrier material arranged to suppress transport of dopant from the doped material into the active region, wherein the barrier material comprises high-Al content AlxGayN, wherein x+y=1, and x?0.50. In a specific aspect, AIN is used as a migration/diffusion barrier layer at a thickness of from about 5 to about 200 Angstroms, to suppress flux of magnesium and/or silicon dopant material into the active region of the III-nitride electronic device, e.g., a UV LED optoelectronic device.Type: GrantFiled: May 6, 2004Date of Patent: October 16, 2007Assignee: Cree, Inc.Inventors: Jeffrey S. Flynn, Huoping Xin, George R. Brandes
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Patent number: 7118813Abstract: A III–V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 ?m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm?2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III–V nitride-based microelectronic and opto-electronic devices.Type: GrantFiled: November 14, 2003Date of Patent: October 10, 2006Assignee: Cree, Inc.Inventors: Xueping Xu, Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes
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Publication number: 20040222431Abstract: A III-nitride electronic device structure including doped material, an active region and a barrier material arranged to suppress transport of dopant from the doped material into the active region, wherein the barrier material comprises high-Al content AlxGayN, wherein x+y=1, and x≧0.50. In a specific aspect, AIN is used as a migration/diffusion barrier layer at a thickness of from about 5 to about 200 Angstroms, to suppress flux of magnesium and/or silicon dopant material into the active region of the III-nitride electronic device, e.g., a UV LED optoelectronic device.Type: ApplicationFiled: May 6, 2004Publication date: November 11, 2004Inventors: Jeffrey S. Flynn, Huoping Xin, George R. Brandes
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Publication number: 20030213964Abstract: A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 102 microns per hour.Type: ApplicationFiled: December 6, 2002Publication date: November 20, 2003Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo, David M. Keogh, Xueping Xu, Barbara E. Landini