Patents by Inventor Jeffrey S. Flynn

Jeffrey S. Flynn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030178633
    Abstract: A Group III-V nitride microelectronic device structure including a delta doped layer and/or a doped superlattice. A delta doping method is described, including the steps of: depositing semiconductor material on a substrate by a first epitaxial film growth process; terminating the deposition of semiconductor material on the substrate to present an epitaxial film surface; delta doping the semiconductor material at the epitaxial film surface, to form a delta doping layer thereon; terminating the delta doping; resuming deposition of semiconductor material to deposit semiconductor material on the delta doping layer, in a second epitaxial film growth process; and continuing the semiconductor material second epitaxial film growth process to a predetermined extent, to form a doped microelectronic device structure, wherein the delta doping layer is internalized in semiconductor material deposited in the first and second epitaxial film growth processes.
    Type: Application
    Filed: March 25, 2002
    Publication date: September 25, 2003
    Inventors: Jeffrey S. Flynn, George R. Brandes
  • Publication number: 20030157376
    Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm−2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 21, 2003
    Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
  • Patent number: 6596079
    Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm−2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: July 22, 2003
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
  • Patent number: 6533874
    Abstract: A method of forming a (gallium, aluminum, indium) nitride base layer on a substrate for subsequent fabrication, e.g., by MOCVD or MBE, of a microelectronic device structure thereon. Vapor-phase (Ga, Al, In) chloride is reacted with a vapor-phase nitrogenous compound in the presence of the substrate, to form (Ga, Al, In) nitride. The (Ga, Al, In) nitride base layer is grown on the substrate by HVPE, to yield a microelectronic device base comprising a substrate with the (Ga, Al, In) nitride base layer thereon. The product of such HVPE process comprises a device quality, single crystal crack-free base layer of (Ga, Al, In) N on the substrate, in which the thickness of the base layer may, for example, be on the order of 2 microns and greater and the defect density of the base layer may, for example, be on the order of 1E8 cm−2 or lower. Microelectronic devices thereby may be formed on the base layer, over a substrate of a foreign (poor lattice match) material, such as sapphire.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: March 18, 2003
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Robert P. Vaudo, Joan M. Redwing, Michael A. Tischler, Duncan W. Brown, Jeffrey S. Flynn
  • Patent number: 6447604
    Abstract: A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: September 10, 2002
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo, David M. Keogh, Xueping Xu, Barbara E. Landini