Abstract: A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface (24) initiates removal of the data from the cache of the identified processor (601). The identified processor (601) initiates a writeback to a memory directory interface unit (24) associated with a home memory 17 for the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22).

Abstract: A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface (24) initiates removal of the data from the cache of the identified processor (601). The identified processor (601) initiates a writeback to a memory directory interface unit (24) associated with a home memory 17 for the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22).

Abstract: An apparatus for high-performance parallel computation, includes plural computation nodes, each having dispatch units, memories in communication with the dispatch units, and processors, each of which is in communication with the memories and the dispatch units. Each dispatch unit is configured to recognize, as ready for execution, one or more computational tasks that have become ready for execution as a result of counted remote writes into the memories. Each of the dispatch units is configured to receive a dispatch request from a processor and to determine whether there exist one or more computational tasks that are both ready and available for execution by the processor.

Abstract: A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface (24) initiates removal of the data from the cache of the identified processor (601). The identified processor (601) initiates a writeback to a memory directory interface unit (24) associated with a home memory 17 for the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22).

Abstract: An apparatus for high-performance parallel computation, includes plural computation nodes, each having dispatch units, memories in communication with the dispatch units, and processors, each of which is in communication with the memories and the dispatch units. Each dispatch unit is configured to recognize, as ready for execution, one or more computational tasks that have become ready for execution as a result of counted remote writes into the memories. Each of the dispatch units is configured to receive a dispatch request from a processor and to determine whether there exist one or more computational tasks that are both ready and available for execution by the processor.

Abstract: A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface (24) initiates removal of the data from the cache of the identified processor (601). The identified processor (601) initiates a writeback to a memory directory interface unit (24) associated with a home memory 17 for the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22).

Abstract: A processor interface (24) receives a flush request from a processor (700) and performs a snoop operation to determine whether the data is maintained in a one of the local processors (700) and whether the data has been modified. If the data is maintained locally and it has been modified, an identified local processor (700) receives the flush request from the processor interface (24) and initiates a writeback to a memory directory interface unit (24). If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22). Memory directory interface unit (22) determines which remote processors within the system (10) have a copy of the data and forwards the flush request only to those identified processors.

Abstract: To efficiently transmit data on a wireless network, small packets that might otherwise be sent individually are aggregated into a “superframe”. This superframe can then be transmitted as a single, larger packet. To form this superframe, a plurality of tagged data packets can be aggregated into a packed aggregation block (PAB). Encapsulation data, e.g. protocol information, can be appended to the PAB. Wireless transmission information can bound the PAB and encapsulation data. Forming the superframe can be performed using an efficient combination of hardware and software. In one embodiment, aggregation of the tagged data packets can be performed by hardware without regard to the underlying protocol(s). Software can then provide protocol-handling support.

Abstract: A transmitting apparatus and method is described that determines, on a frame-by-frame basis, whether to transmit a compressed frame or a non-compressed frame, depending upon whether the compressed frame or the non-compressed frame will actually be smaller in size. The frame that is smaller is indicated for transmission, with a header of the frame being adapted to include a compression flag indicating whether that frame is the compressed or the non-compressed frame. After wireless transmission and reception, the received frame is, if needed, decompressed if so indicated by the compression flag.

Abstract: A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.

Abstract: A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.

Abstract: A processor (500) issues a read request for data. A processor interface (24) initiates a local search for the requested data and also forwards the read request to a memory directory (24) for processing. While the read request is processing, the processor interface (24) can determine if the data is available locally. If so, the data is transferred to the processor (500) for its use. The memory directory (24) processes the read request and generates a read response therefrom. The processor interface (24) receives the read response and determines whether the data was available locally. If so, the read response is discarded. If the data was not available locally, the processor interface (24) provides the read response to the processor (500).

Abstract: A processor (100) in a distributed shared memory computer system (10) receives ownership of data and initiates an initial update to memory request. A front side bus processor interface (24) forwards the initial update to memory request to a memory directory interface unit (22). The front side processor interface (24) may receive subsequent update to memory requests for the data from processors co-located on the same local bus. Front side bus processor interface (24) maintains a most recent subsequent update to memory in a queue (102). Once the data has been updated in its home memory (17), the memory directory interface unit (22) sends a writeback acknowledge to the front side bus processor interface (24). The most recent subsequent update to memory request in the queue (102) is then forwarded by the front side bus processor interface (24) to the memory directory interface unit (24) for processing.

Abstract: A partitioned computer system (32) includes a plurality of node controllers (12) connected by a network (14) and partitioned into a plurality of partitioned groups (40). A requesting node controller (34) in one partitioned group (40) requests a latest copy of a line in a memory (17) in a separate partitioned group (40). A storing node controller (36) in the separate partitioned group (40) holding the latest copy of the line in its memory (17) is identified. The requesting node controller (34) transmits its request for a coherent copy of a line to the storing node controller (36). The storing node controller (36) transmits the latest copy of the line in response to the request to the requesting node controller (34) without including the requester in a sharer-tracking process.

Abstract: A multiprocessor system and method includes a processing sub-system including a plurality of processors and a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store a copy of data from the processor memory system for use by a corresponding peripheral device and to delete the copy at a first time event. A directory for the processor is operable to identify the data as owned upon providing the copy to the I/O sub-system and to identify the data as unowned at a second time event.

Abstract: A processor (300) in a distributed shared memory system (10) has ownership of a cache line. The processor modifies the cache line and wishes to update the home memory (17) of the cache line with the modification. The processor (300) generates a return request for routing by a processor interface (24). Meanwhile, a second processor (400) wishes to obtain ownership of the cache line and sends a read request to a memory directory (22) associated with the home memory (17) of the cache line. The memory directory (22) generates an intervention request towards the processor interface (24) corresponding to the last known location of the cache line. The processor interface (24) has now forwarded the return request to the memory directory (22) but subsequent to the read request from the second processor (400).

Abstract: A multiprocessor system and method includes a processing sub-system including a plurality of processors in a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store exclusive read-only copies of data from the processor memory system for use by a corresponding peripheral device.

Abstract: A transmitting apparatus and method is described that determines, on a frame-by-frame basis, whether to transmit a compressed frame or a non-compressed frame, depending upon whether the compressed frame or the non-compressed frame will actually be smaller in size. The frame that is smaller is indicated for transmission, with a header of the frame being adapted to include a compression flag indicating whether that frame is the compressed or the non-compressed frame. After wireless transmission and reception, the received frame is, if needed, decompressed if so indicated by the compression flag.

Abstract: A memory device and method which provide at least one memory segment. The memory segment includes at least one first portion which is configured to store data. The memory segment also includes at least one second portion associated with the first portion, and which is configured to store directory information for at least one cache line thereon.

Abstract: A multi-processor system (10) includes a plurality of processors (12). Each processor (12) has an integrated memory (16) operable to provide, receive, and store data. Each processor (12) also includes an integrated memory controller (30) in order to control read and write access to the integrated memory (16). Additionally, each processor (12) includes an integrated memory directory (18) operable to maintain a plurality of memory references to data within the integrated memory (16). The multi-processor system (10) also includes an external switch (14) coupled to each of the plurality of processors (12). The external switch (14) passes data to and from any of the plurality of processors (12). The external switch (14) has an external directory (22). The external directory (22) provides a memory reference for each of the plurality of processors (12) to remote data that is not provided within its own integrated memory directory (18).