Abstract: A multiprocessor computer system includes a method and system of handling invalidation requests to a plurality of alias processors not sharing a line of memory in a computer system. A memory directory interface unit receives an invalidation request for a shared line of memory shared in a plurality of sharing processors. A superset of processors in the computer system that includes each of the sharing processors is determined that includes at least one alias processor not sharing the shared line of memory. An invalidation message is transmitted to each processor in the superset of processors. The number Na of alias processors in the superset of processors is determined and a superacknowledgement message is provided that is equivalent to acknowledging receipt of Na invalidation messages.

Abstract: A processor (500) issues a read request for data. A processor interface (24) initiates a local search for the requested data and also forwards the read request to a memory directory (24) for processing. While the read request is processing, the processor interface (24) can determine if the data is available locally. If so, the data is transferred to the processor (500) for its use. The memory directory (24) processes the read request and generates a read response therefrom. The processor interface (24) receives the read response and determines whether the data was available locally. If so, the read response is discarded. If the data was not available locally, the processor interface (24) provides the read response to the processor (500).

Abstract: In a preferred embodiment is described a scheduling architecture, including a plurality of queues each within an associated queue control unit, and a plurality of data control units. The queue control units are directed to operations that obtain data for transmission of a stream from a host and ensure that it is available for transmission, preferably as a single stream. The data control units are each directed to operations that format the data from the queue control units in dependence upon the transmission (or channel) characteristics that are to be associated with that data. Further, each queue control unit can configurably be input to any of the data control units. In one embodiment the output of each of the data control units is controlled by a data arbiter, so that a single stream of data is obtained.

Abstract: A multi-processor system (10) includes a plurality of processors (12). Each processor (12) has an integrated memory (16) operable to provide, receive, and store data. Each processor (12) also includes an integrated memory controller (30) in order to control read and write access to the integrated memory (16). Additionally, each processor (12) includes an integrated memory directory (18) operable to maintain a plurality of memory references to data within the integrated memory (16). The multi-processor system (10) also includes an external switch (14) coupled to each of the plurality of processors (12). The external switch (14) passes data to and from any of the plurality of processors (12). The external switch (14) has an external directory (22). The external directory (22) provides a memory reference for each of the plurality of processors (12) to remote data that is not provided within its own integrated memory directory (18).

Abstract: A memory device and method which provide at least one memory segment. The memory segment includes at least one first portion which is configured to store data. The memory segment also includes at least one second portion associated with the first portion, and which is configured to store directory information for at least one cache line thereon.