Patents by Inventor Jeffrey Scott Brown
Jeffrey Scott Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8721748Abstract: A downdraft gasifier that utilizes a plurality of vertically positioned tubes to create a pyrolysis zone, an oxidation zone beneath the pyrolysis zone and a reduction zone beneath the oxidation zone. The shape of the tubes eliminates the need for a restriction (hearth), which limits the maximum achievable throughput. A rotating and vertically adjustable grate is located beneath, but not attached to, the reduction zone of the gasifier.Type: GrantFiled: January 28, 2013Date of Patent: May 13, 2014Assignee: PHG Energy, LLCInventors: Deon John Potgieter, Billy Freeman Hopper, Jeffrey Scott Brown, Mark Oliver Loftin
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Patent number: 8667438Abstract: Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions.Type: GrantFiled: February 7, 2013Date of Patent: March 4, 2014Assignee: LSI CorporationInventor: Jeffrey Scott Brown
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Patent number: 8546636Abstract: A method of gasification using a downdraft gasifier having a plurality of vertically positioned tubes to create a pyrolysis zone, an oxidation zone beneath the pyrolysis zone and a reduction zone beneath the oxidation zone. The shape of the tubes eliminates the need for a restriction (hearth) in the gasifier, which limits the maximum achievable throughput. A rotating and vertically adjustable grate is located beneath, but not attached to, the reduction zone of the gasifier.Type: GrantFiled: January 28, 2013Date of Patent: October 1, 2013Assignee: PHG Energy, LLCInventors: Deon John Potgieter, Billy Freeman Hopper, Jeffrey Scott Brown, Mark Oliver Loftin
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Patent number: 8418102Abstract: Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions.Type: GrantFiled: April 29, 2008Date of Patent: April 9, 2013Assignee: LSI CorporationInventor: Jeffrey Scott Brown
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Patent number: 7746722Abstract: A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.Type: GrantFiled: June 17, 2008Date of Patent: June 29, 2010Assignee: LSI CorporationInventors: Jeffrey Scott Brown, Chang Jung
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Publication number: 20090267671Abstract: Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions.Type: ApplicationFiled: April 29, 2008Publication date: October 29, 2009Inventor: Jeffrey Scott Brown
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Publication number: 20080253206Abstract: A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.Type: ApplicationFiled: June 17, 2008Publication date: October 16, 2008Inventors: Jeffrey Scott Brown, Chang Jung
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Patent number: 7400543Abstract: A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.Type: GrantFiled: November 12, 2003Date of Patent: July 15, 2008Assignee: LSI Logic CorporationInventors: Jeffrey Scott Brown, Chang Jung
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Patent number: 7143386Abstract: A pre-diffused array of core memory cells is provided in a metal programmable device. Multiple control block versions of interface logic are also provided and placed around the memory core. Contact points for each control block are brought to the surface of the wafer using a via. The appropriate interface logic is selected by connecting the metal layer to the appropriate surface contacts to access the core memory cells. The application-specific circuit, including memory configuration and memory interface type, is programmed with the metal layer.Type: GrantFiled: August 19, 2003Date of Patent: November 28, 2006Assignee: LSI Logic CorporationInventor: Jeffrey Scott Brown
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Patent number: 6963515Abstract: The present invention is a method and system for providing a scalable memory building block device. The memory building block device includes a plurality of separate memory arrays, decode logic for selecting only one bit from the plurality of memory arrays, and output means for providing only one bit as an output of the memory building block device, such that the memory building block device generates as its output only one bit.Type: GrantFiled: May 8, 2003Date of Patent: November 8, 2005Assignee: LSI Logic CorporationInventors: Jeffrey Scott Brown, Craig R. Chafin, Chang Ho Jung
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Publication number: 20040223398Abstract: The present invention is a method and system for providing a scalable memory building block device. The memory building block device includes a plurality of separate memory arrays, decode logic for selecting only one bit from the plurality of memory arrays, and output means for providing only one bit as an output of the memory building block device, such that the memory building block device generates as its output only one bit.Type: ApplicationFiled: May 8, 2003Publication date: November 11, 2004Inventors: Jeffrey Scott Brown, Craig R. Chafin, Chang Ho Jung
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Patent number: 6774017Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.Type: GrantFiled: July 3, 2002Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Andres Bryant, Robert J. Gauthier, Jr., Randy William Mann, Steven Howard Voldman
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Patent number: 6614124Abstract: An SRAM memory cell device comprises wordline and bitline inputs for enabling read/write access to memory cell contents, and, a diffusion region for maintaining a voltage to preserve memory cell content when the cell is not being accessed. The device further comprises a transistor device having a gate input for receiving a wordline voltage to turn off the transistor device when not performing memory cell read/write access; and, a gate oxide layer formed under the transistor device gate exhibiting resistance property for leaking current therethrough when the wordline voltage is applied to the gate input and the transistor device is off. The diffusion region receives voltage derived from the wordline voltage applied to said gate input to enable retention of said memory cell content in the absence of applied bitline voltage to thereby reduce power consumption.Type: GrantFiled: November 28, 2000Date of Patent: September 2, 2003Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Chung Hon Lam, Randy William Mann
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Patent number: 6486510Abstract: A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and drain of the FET. The germanium can be implanted prior to gate and source and drain formation, and reduces the reverse short channel effect normally seen in FETs. The short channel effect normally occurring in FETs is not negatively impacted by the germanium implant.Type: GrantFiled: November 12, 2001Date of Patent: November 26, 2002Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Stephen Scott Furkay, Robert J. Gauthier, Jr., Dale Warner Martin, James Albert Slinkman
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Publication number: 20020167050Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.Type: ApplicationFiled: July 3, 2002Publication date: November 14, 2002Inventors: Jeffrey Scott Brown, Andres Bryant, Robert J. Gauthier, Randy William Mann, Steven Howard Voldman
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Patent number: 6476445Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.Type: GrantFiled: April 30, 1999Date of Patent: November 5, 2002Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Andres Bryant, Robert J. Gauthier, Jr., Randy William Mann, Steven Howard Voldman
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Publication number: 20020063294Abstract: A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and drain of the FET. The germanium can be implanted prior to gate and source and drain formation, and reduces the reverse short channel effect normally seen in FETs. The short channel effect normally occurring in FETs is not negatively impacted by the germanium implant.Type: ApplicationFiled: November 12, 2001Publication date: May 30, 2002Applicant: INTERNATIONAL BUSINESS MACHINESInventors: Jeffrey Scott Brown, Stephen Scott Furkay, Robert J. Gauthier, Dale Warner Martin, James Albert Slinkman
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Patent number: 6352912Abstract: A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and drain of the FET. The germanium can be implanted prior to gate and source and drain formation, and reduces the reverse short channel effect normally seen in FETs. The short channel effect normally occurring in FETs is not negatively impacted by the germanium implant.Type: GrantFiled: March 30, 2000Date of Patent: March 5, 2002Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Stephen Scott Furkay, Robert J. Gauthier, Jr., Dale Warner Martin, James Albert Slinkman
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Patent number: 6294419Abstract: A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.Type: GrantFiled: November 6, 2000Date of Patent: September 25, 2001Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Robert J. Gauthier, Jr., Randy William Mann, Steven Howard Voldman
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Patent number: 6281593Abstract: A body contact to a SOI device is created by providing a deeper buried oxide region for providing connection to the FET body.Type: GrantFiled: December 6, 1999Date of Patent: August 28, 2001Assignee: International Business Machines CorporationInventors: Jeffrey Scott Brown, Andres Bryant, Robert J. Gauthier, Jr., Steven Howard Voldman