Abstract: An orthodontic appliance includes features for reducing friction between an interior of an archwire slot portion of the appliance and an archwire to be placed within the archwire slot. Other embodiments include a rounded exterior occlusal surface. Embodiments further include one or more receptacles for receiving an installation tool.

Abstract: A method of forming a nanowire device includes providing a substrate containing nanowires between vertical spacers, selectively depositing a high-k film on the nanowires relative to the vertical spacers, and selectively depositing a metal-containing gate electrode layer on the high-k film relative to the vertical spacers. The method can further include selectively depositing a dielectric material on the vertical spacers prior to selectively depositing the high-k film, where the dielectric material has a lower dielectric constant than the high-k film.

Abstract: A neuromodulation catheter is positionable in a blood vessel having a wall for use in delivering therapeutic energy to targets external to the blood vessel. An electrically insulative substrate such as an elongate finger is carried at a distal end of the catheter body. The substrate has a first face carrying a plurality of electrodes, and a second face on an opposite side of the substrate from the first face. The finger is biased such that when expanded within the blood vessel, it forms a spiral configuration with the first face facing outwardly to bias the electrodes in contact with the blood vessel wall.

Abstract: A urinal assembly having a frame and a plurality of posts or posts extending from the frame. The frame can include a plurality of openings. The openings can be defined by a plurality of sides and corners. The posts can extend from the corners and/or from the sides of the openings. In some embodiments, posts extend from a first face and a second face of the frame.

Abstract: A method of fabricating a semiconductor device includes providing a substrate having a layered fin structure thereon. The layered fin structure includes base fin portion, a sacrificial portion provided on the base fin portion and a channel portion provided on the sacrificial portion. A doping source film is provided on the substrate over the layered fin structure, and diffusing doping materials from the doping source film into a portion of the layered fin structure other than the channel portion to form a diffusion doped region in the layered fin structure. An isolation material is provided on the substrate over at least the diffusion doped region of the layered fin structure.

Abstract: A light emitting diode (LED) shielding and monitoring system includes multiple light emitting diodes (LEDs) (12, 14, 82, 92), multiple optical detectors (20, 84, 94) for detecting a light output of the plurality of LEDs (12, 14, 82, 92), and a LED shield (30, 110) with multiple compartments (38, 114) for receiving the multiple optical detectors (20, 84, 94). The LED shield (30, 110) is configured such that each compartment (38, 114) receives an optical detector (20, 84, 94), and wherein each compartment (38, 114) is configured such that the optical detector (20, 84, 94) within the compartment (38, 114) detects the light output of a LED (12, 14, 82, 92) of the multiple LEDs (12, 14, 82, 92) without detecting light output other than the light output of the LED (12, 14, 82, 92). Further, wayside LED signals including a LED shielding and monitoring system are provided.

Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space.

Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space.

Abstract: A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.

Abstract: Techniques herein include processes and systems by which a reproducible CD variation pattern can be mitigated or corrected to yield desirable CDs from microfabrication patterning processes, via resolution enhancement. A repeatable portion of CD variation across a set of wafers is identified, and then a correction exposure pattern is generated. A direct-write projection system exposes this correction pattern on a substrate as a component exposure, augmentation exposure, or partial exposure. A conventional mask-based photolithographic system executes a primary patterning exposure as a second or main component exposure. The two component exposures when combined enhance resolution of the patterning exposure to improve CDs on the substrate being processed without measure each wafer.

Abstract: Techniques herein include methods of tuning film thickness of a dispensed resist or solvent. Techniques herein include controlling a final thickness of a resist film by manipulating substrate spin speed, viscosity of photoresist, amount of solids within a photoresist, and solvent evaporation rates in real time from a dispense module. This includes mixing a higher-concentration photoresist with a dilution fluid proximate to a dispense nozzle just before deposition on a substrate. An amount of dilution fluid added can be calculated to result in a photoresist concentration or viscosity to result in a film of a desired thickness.

Abstract: A semiconductor device includes a plurality of first sources/drains and a plurality of first source/drain (S/D) contacts formed over the first sources/drains. The device also includes a plurality of first dielectric caps. Each of the plurality of first dielectric caps is positioned over a respective first S/D contact to cover a top portion and at least a part of side portions of the respective first S/D contact. The device also includes a plurality of second sources/drains and a plurality of second S/D contacts that are staggered over the plurality of first S/D contacts so as to form a stair-case configuration. A plurality of second dielectric caps are formed over the plurality of second S/D contacts. Each of the plurality of second dielectric caps is positioned over a respective second S/D contact to cover a top portion and at least a part of side portions of the respective second S/D contact.

Abstract: A composite wood product in accordance with a particular embodiment of the present technology includes a composite substrate and a sealant disposed within a surface portion of the substrate. The substrate includes wood and a binder. The sealant includes photoresponsive molecules present within the surface portion of the substrate at an average concentration greater than 1000 parts per million. In response to a 120-day exposure at 7 inches separation distance to a UV lamp with a UVA (315-400 nm) output of 13.6 W and a UVB (280-315 nm) output of 3.0 W, a CIELab b* value of the substrate decreases by a first amount, a CIELab b* value of the sealant increases by a second amount, and a CIELab b* value of the overall wood product decreases by an amount less than the first amount, increases by an amount less than the second amount, or is unchanged.

Abstract: An orthodontic appliance includes features for reducing friction between an interior of an archwire slot portion of the appliance and an archwire to be placed within the archwire slot. Other embodiments include a rounded exterior occlusal surface. Embodiments further include one or more receptacles for receiving an installation tool.

Abstract: A urinal assembly having a frame and a plurality of posts or posts extending from the frame. The frame can include a plurality of openings. The openings can be defined by a plurality of sides and corners. The posts can extend from the corners and/or from the sides of the openings. In some embodiments, posts extend from a first face and a second face of the frame.

Abstract: A system and method for mobile social networking within a target area are provided. The method provides for mobile social networking. The method includes receiving a social networking profile, and a target area. The social networking profile has at least one user preference. The method also includes broadcasting the social networking profile to one or more members of the social network within the target area. The method further includes searching within the target area for the one or more members having a preference that is the same or similar to the at least one user preference. The method additionally includes enabling contact with the one or more members having the same or similar at least one user preference.

Abstract: A semiconductor device includes a substrate having a working surface, and a plurality of field effect transistor (FET) devices provided on the substrate in a common plane along the working surface. Each FET device includes an active nanochannel structure having opposing end surfaces and a sidewall surface extending between the opposing end surfaces, and an active gate structure surrounding an intermediate portion of the nanochannel structure in contact with the sidewall surface. First and second gate spacers each surrounding a respective end portion of the nanochannel structure in contact with the side wall surface, and first and second source/drain (S/D) structures are in contact with the opposing end surfaces of the nanochannel structure respectively. A single diffusion break provided between first and second FET devices, the single diffusion break including a dummy nanochannel structure connected to an S/D structure of the first FET device and an S/D structure of the second FET device.

Abstract: A system and method for mobile social networking within a target area are provided. The method provides for mobile social networking. The method includes receiving a social networking profile, and a target area. The social networking profile has at least one user preference. The method also includes broadcasting the social networking profile to one or more members of the social network within the target area. The method further includes searching within the target area for the one or more members having a preference that is the same or similar to the at least one user preference. The method additionally includes enabling contact with the one or more members having the same or similar at least one user preference.

Abstract: A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.