Patents by Inventor Jeffrey Smith

Jeffrey Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for intra-abdominally moving an organ
    Patent number: 10524773
    Abstract: A surgical tissue connector system for moving a first internal body tissue to a position away from a second internal body tissue and then holding the first internal body tissue in the position. Tissue connectors are secured to cords such that the length of cord between the tissue connectors can be easily adjusted in a laparoscopic work space.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: January 7, 2020
    Assignee: Freehold Surgical, Inc.
    Inventors: J. Stephen Scott, Jeffrey Smith
  • INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME
    Publication number: 20200006129
    Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.
    Type: Application
    Filed: September 5, 2019
    Publication date: January 2, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Soo Doo CHAE, Jeffrey SMITH, Gerrit J. LEUSINK, Robert D. CLARK, Kai-Hung YU
  • Reduced-Friction Buccal Tube and Method of Use
    Publication number: 20200000556
    Abstract: An orthodontic appliance includes features for reducing friction between an interior of an archwire slot portion of the appliance and an archwire to be placed within the archwire slot. Other embodiments include a rounded exterior occlusal surface. Embodiments further include one or more receptacles for receiving an installation tool.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Applicant: RMO, Inc.
    Inventors: Jeffrey Smith, Leon W. Laub
  • FULLY SELF-ALIGNED VIA WITH SELECTIVE BILAYER DIELECTRIC REGROWTH
    Publication number: 20200006140
    Abstract: In a method for processing a substrate, a conductive cap layer is selectively formed over a plurality of conductive structures that are positioned in a first dielectric layer. A second dielectric layer is selectively formed over the first dielectric layer. A third dielectric layer is selectively formed over the second dielectric layer. A fourth dielectric layer is then formed over the plurality of conductive structures and the third dielectric layer, and an interconnect structure is subsequently formed within the fourth dielectric layer. The interconnect structure includes a via structure that has a first portion positioned over the conductive cap layer so that sidewalls of the first portion are surrounded by the third dielectric layer, and a second portion disposed over the first portion and the third dielectric layer.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 2, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Kandabara TAPILY, Jeffrey SMITH
  • METHOD FOR FORMING A NANOWIRE DEVICE
    Publication number: 20190393097
    Abstract: A method of forming a nanowire device includes providing a substrate containing nanowires between vertical spacers, selectively depositing a high-k film on the nanowires relative to the vertical spacers, and selectively depositing a metal-containing gate electrode layer on the high-k film relative to the vertical spacers. The method can further include selectively depositing a dielectric material on the vertical spacers prior to selectively depositing the high-k film, where the dielectric material has a lower dielectric constant than the high-k film.
    Type: Application
    Filed: June 21, 2019
    Publication date: December 26, 2019
    Inventors: Kandabara Tapily, Jeffrey Smith, Gerrit Leusink
  • Intravascular Electrode Arrays for Neuromodulation
    Publication number: 20190374778
    Abstract: A neuromodulation catheter is positionable in a blood vessel having a wall for use in delivering therapeutic energy to targets external to the blood vessel. An electrically insulative substrate such as an elongate finger is carried at a distal end of the catheter body. The substrate has a first face carrying a plurality of electrodes, and a second face on an opposite side of the substrate from the first face. The finger is biased such that when expanded within the blood vessel, it forms a spiral configuration with the first face facing outwardly to bias the electrodes in contact with the blood vessel wall.
    Type: Application
    Filed: August 8, 2019
    Publication date: December 12, 2019
    Applicant: Interventional Autonomics Corporation
    Inventors: Stephen C. Masson, Jeffrey A. Smith
  • Urinal screens
    Patent number: 10501924
    Abstract: A urinal assembly having a frame and a plurality of posts or posts extending from the frame. The frame can include a plurality of openings. The openings can be defined by a plurality of sides and corners. The posts can extend from the corners and/or from the sides of the openings. In some embodiments, posts extend from a first face and a second face of the frame.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: December 10, 2019
    Assignee: Fresh Products, Inc.
    Inventors: Douglas S. Brown, Jeffrey A. Smith
  • Method of preventing bulk silicon charge transfer for nanowire and nanoslab processing
    Patent number: 10490630
    Abstract: A method of fabricating a semiconductor device includes providing a substrate having a layered fin structure thereon. The layered fin structure includes base fin portion, a sacrificial portion provided on the base fin portion and a channel portion provided on the sacrificial portion. A doping source film is provided on the substrate over the layered fin structure, and diffusing doping materials from the doping source film into a portion of the layered fin structure other than the channel portion to form a diffusion doped region in the layered fin structure. An isolation material is provided on the substrate over at least the diffusion doped region of the layered fin structure.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: November 26, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton deVilliers
  • LED SHIELDING AND MONITORING SYSTEM AND WAYSIDE LED SIGNALS
    Publication number: 20190329802
    Abstract: A light emitting diode (LED) shielding and monitoring system includes multiple light emitting diodes (LEDs) (12, 14, 82, 92), multiple optical detectors (20, 84, 94) for detecting a light output of the plurality of LEDs (12, 14, 82, 92), and a LED shield (30, 110) with multiple compartments (38, 114) for receiving the multiple optical detectors (20, 84, 94). The LED shield (30, 110) is configured such that each compartment (38, 114) receives an optical detector (20, 84, 94), and wherein each compartment (38, 114) is configured such that the optical detector (20, 84, 94) within the compartment (38, 114) detects the light output of a LED (12, 14, 82, 92) of the multiple LEDs (12, 14, 82, 92) without detecting light output other than the light output of the LED (12, 14, 82, 92). Further, wayside LED signals including a LED shielding and monitoring system are provided.
    Type: Application
    Filed: June 28, 2016
    Publication date: October 31, 2019
    Inventors: Axel Beier, Jeffrey Smith
  • THREE-DIMENSIONAL SEMICONDUCTOR DEVICE INCLUDING INTEGRATED CIRCUIT, TRANSISTORS AND TRANSISTOR COMPONENTS AND METHOD OF FABRICATION
    Publication number: 20190326301
    Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 24, 2019
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey SMITH, Anton J. deVilliers
  • Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabrication
    Patent number: 10453850
    Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: October 22, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton deVilliers
  • METHOD OF FORMING GATE SPACER FOR NANOWIRE FET DEVICE
    Publication number: 20190296128
    Abstract: A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 26, 2019
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey SMITH, Anton deVILLIERS
  • Critical Dimension Correction Via Calibrated Trim Dosing
    Publication number: 20190287795
    Abstract: Techniques herein include processes and systems by which a reproducible CD variation pattern can be mitigated or corrected to yield desirable CDs from microfabrication patterning processes, via resolution enhancement. A repeatable portion of CD variation across a set of wafers is identified, and then a correction exposure pattern is generated. A direct-write projection system exposes this correction pattern on a substrate as a component exposure, augmentation exposure, or partial exposure. A conventional mask-based photolithographic system executes a primary patterning exposure as a second or main component exposure. The two component exposures when combined enhance resolution of the patterning exposure to improve CDs on the substrate being processed without measure each wafer.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 19, 2019
    Inventors: Anton deVilliers, Ronald Nasman, Jeffrey Smith
  • System and Method for Tuning Thickness of Resist Films
    Publication number: 20190287793
    Abstract: Techniques herein include methods of tuning film thickness of a dispensed resist or solvent. Techniques herein include controlling a final thickness of a resist film by manipulating substrate spin speed, viscosity of photoresist, amount of solids within a photoresist, and solvent evaporation rates in real time from a dispense module. This includes mixing a higher-concentration photoresist with a dilution fluid proximate to a dispense nozzle just before deposition on a substrate. An amount of dilution fluid added can be calculated to result in a photoresist concentration or viscosity to result in a film of a desired thickness.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 19, 2019
    Inventors: Anton J. deVilliers, Jeffrey Smith, Daniel Fulford
  • THREE-DIMENSIONAL DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20190288004
    Abstract: A semiconductor device includes a plurality of first sources/drains and a plurality of first source/drain (S/D) contacts formed over the first sources/drains. The device also includes a plurality of first dielectric caps. Each of the plurality of first dielectric caps is positioned over a respective first S/D contact to cover a top portion and at least a part of side portions of the respective first S/D contact. The device also includes a plurality of second sources/drains and a plurality of second S/D contacts that are staggered over the plurality of first S/D contacts so as to form a stair-case configuration. A plurality of second dielectric caps are formed over the plurality of second S/D contacts. Each of the plurality of second dielectric caps is positioned over a respective second S/D contact to cover a top portion and at least a part of side portions of the respective second S/D contact.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 19, 2019
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey SMITH, Anton deVilliers, Kandabara Tapily, Jodi Grzeskowiak, Kai-Hung Yu
  • Wood products with enhanced resistance to graying and water infiltration and related technology
    Patent number: 10414945
    Abstract: A composite wood product in accordance with a particular embodiment of the present technology includes a composite substrate and a sealant disposed within a surface portion of the substrate. The substrate includes wood and a binder. The sealant includes photoresponsive molecules present within the surface portion of the substrate at an average concentration greater than 1000 parts per million. In response to a 120-day exposure at 7 inches separation distance to a UV lamp with a UVA (315-400 nm) output of 13.6 W and a UVB (280-315 nm) output of 3.0 W, a CIELab b* value of the substrate decreases by a first amount, a CIELab b* value of the sealant increases by a second amount, and a CIELab b* value of the overall wood product decreases by an amount less than the first amount, increases by an amount less than the second amount, or is unchanged.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: September 17, 2019
    Assignee: Weyerhaeuser NR Company
    Inventors: Jack G. Winterowd, Erik M. Parker, Glen D. Robak, Jeffrey Smith, William D. Brady
  • Reduced-friction buccal tube and method of use
    Patent number: 10405950
    Abstract: An orthodontic appliance includes features for reducing friction between an interior of an archwire slot portion of the appliance and an archwire to be placed within the archwire slot. Other embodiments include a rounded exterior occlusal surface. Embodiments further include one or more receptacles for receiving an installation tool.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: September 10, 2019
    Assignee: RMO, Inc.
    Inventors: Jeffrey Smith, Leon W. Laub
  • URINAL SCREENS
    Publication number: 20190264435
    Abstract: A urinal assembly having a frame and a plurality of posts or posts extending from the frame. The frame can include a plurality of openings. The openings can be defined by a plurality of sides and corners. The posts can extend from the corners and/or from the sides of the openings. In some embodiments, posts extend from a first face and a second face of the frame.
    Type: Application
    Filed: October 30, 2018
    Publication date: August 29, 2019
    Inventors: Douglas S. Brown, Jeffrey A. Smith
  • SYSTEM AND METHOD FOR MOBILE SOCIAL NETWORKING WITHIN A TARGET AREA
    Publication number: 20190266524
    Abstract: A system and method for mobile social networking within a target area are provided. The method provides for mobile social networking. The method includes receiving a social networking profile, and a target area. The social networking profile has at least one user preference. The method also includes broadcasting the social networking profile to one or more members of the social network within the target area. The method further includes searching within the target area for the one or more members having a preference that is the same or similar to the at least one user preference. The method additionally includes enabling contact with the one or more members having the same or similar at least one user preference.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Inventors: Frederick Joel Mason, JR., Donald Jeffrey Smith
  • Urinal screen
    Patent number: D857181
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: August 20, 2019
    Assignee: FRESH PRODUCTS, INC.
    Inventors: Douglas S. Brown, Jeffrey A. Smith