Abstract: A coding scheme for data is presented in which data is encoded and decoded such that a sequence of unconstrained input binary symbols, such as 1's and 0's, is encoded into a representation according to an alphabet comprising allowable time intervals between adjacent input binary symbols according to a precision parameter p, a minimum resolution parameter ?, and resolution restriction functions L(t) and R(t), thereby defining a precision-resolution (PR) constrained code, and is modulated into an output signal comprising a waveform having signal peaks corresponding to the representation and separated according to the PR-constrained code for transmission of the output signal over the data channel. In this discussion, the minimum resolution parameter is denoted as a and is not limited to integer values.

Abstract: Systems and methods, including computer software products, can be used to update or modify data stored in a memory. One or more variables are represented with one or more cell values in a memory. Each variable is associated with one or more of the cell values. Multiple states of the one or more variables are defined, and each defined state of the one or more variables includes a current store value for each variable and at least one previous store value for the variable. One or more single cell values influence the current store value and previous store value of at least one variable.

Abstract: Error correction is tailored for the use of an ECC for correcting asymmetric errors with low magnitude in a data device, with minimal modifications to the conventional data device architecture. The technique permits error correction and data recovery to be performed with reduced-size error correcting code alphabets. For particular cases, the technique can reduce the problem of constructing codes for correcting limited magnitude asymmetric errors to the problem of constructing codes for symmetric errors over small alphabets. Also described are speed up techniques for reaching target data levels more quickly, using more aggressive memory programming operations.

Abstract: Systems and methods, including computer software products, can be implemented for updating or modifying stored data. Multiple variables are represented by one or more cell values in a memory. Each variable is associated with one or more of the cell values and at least one single cell value influences a value of at least two of the variables. Multiple states of the multiple variables are defined. At least one of the multiple defined states of the multiple variables is associated with more than one set of cell values.

Abstract: A distributed gateway for controlling computer network data traffic dynamically reconfigures traffic assignments among multiple gateway machines for increased network availability. If one of the distributed gateway machines becomes unavailable, traffic assignments are moved among the multiple machines such that network availability is substantially unchanged. The machines of the distributed gateway form a cluster and communicate with each other using a Group Membership protocol word such that automatic, dynamic traffic assignment reconfiguration occurs in response to machines being added and deleted from the cluster, with no loss in functionality for the gateway overall, in a process that is transparent to network users, thereby providing a distributed gateway functionality that is scalable. Operation of the distributed gateway remains consistent as machines are added and deleted from the cluster.

Abstract: A distributed gateway for controlling computer network data traffic dynamically reconfigures traffic assignments among multiple gateway machines for increased network availability. If one of the distributed gateway machines becomes unavailable, traffic assignments are moved among the multiple machines such that network availability is substantially unchanged. The machines of the distributed gateway form a cluster and communicate with each other using a Group Membership protocol word such that automatic, dynamic traffic assignment reconfiguration occurs in response to machines being added and deleted from the cluster, with no loss in functionality for the gateway overall, in a process that is transparent to network users, thereby providing a distributed gateway functionality that is scalable. Operation of the distributed gateway remains consistent as machines are added and deleted from the cluster.

Abstract: A method for the synthesis of multi-level combinational circuits with cyclic topologies. The techniques, applicable in logic synthesis, and in particular in the structuring phase of logic synthesis, optimize a multi-level description, introducing feedback and potentially optimizing the network.

Abstract: A coding scheme for data is presented in which data is encoded and decoded such that a sequence of unconstrained input binary symbols, such as 1's and 0's, is encoded into a representation according to an alphabet comprising allowable time intervals between adjacent input binary symbols according to a precision parameter p, a minimum resolution parameter ?, and resolution restriction functions L(t) and R(t), thereby defining a precision-resolution (PR) constrained code, and is modulated into an output signal comprising a waveform having signal peaks corresponding to the representation and separated according to the PR-constrained code for transmission of the output signal over the data channel. In this discussion, the minimum resolution parameter is denoted as a and is not limited to integer values.

Abstract: Routing in a wireless network of communication devices that are located within a network boundary moves network traffic from a first communication device to a second communication device. A geometric indicator of network connectivity is constructed that identifies a curve on which network nodes are located and a network location for each node of the wireless network is determined, so that the network location of a node p identifies a node on the geometric indicator curve that is closest to the node p and indicates connectivity from the node p to the closest node of the geometric indicator curve. A routing scheme is determined, to route in the wireless network from the first communication device to the second communication device based on the respective determined network locations for the first and second communication devices.

Abstract: The design of communication and storage systems requires a choice of modulation and coding. In conventional storage and communication systems, the commonly used modulation scheme is called Non Return to Zero (NRZ) and the commonly used codes are called Run Length Limited (RLL) codes. The disclosure describes a new modulation scheme that can be used to increase the data transmission rate or storage density. The disclosure also describes codes that are referred to as Interval Modulation Codes, which can be used to transmit or store information efficiently using the new modulation scheme. Also described are procedures for determining if there exist suitable Interval Modulation Codes, given predetermined parameters that describe their desired performance. The disclosure also describes procedures or algorithms for constructing optimal Interval Modulation Codes given a set of parameters that describe their performance. The described techniques can be used in different communication (e.g.

Abstract: A method of transmitting data packets, where randomness is added to the schedule. Universal broadcast schedules using encoding and randomization techniques are also discussed, together with optimal randomized schedules and an approximation algorithm for finding near-optimal schedules.

Abstract: A scalable, distributed, highly available, load balancing server system having multiple machines is provided that functions as a front server layer between a network (such as the Internet) and a back-end server layer having multiple machines functioning as Web file servers, FTP servers, or other application servers. The front layer machines comprise a server cluster that performs fail-over and dynamic load balancing for both server layers. The operation of the servers on both layers is monitored, and when a server failure at either layer is detected, the system automatically shifts network traffic from the failed machine to one or more operational machines, reconfiguring front-layer servers as needed without interrupting operation of the server system. The server system automatically accommodates additional machines in the server cluster, without service interruption. The system operates with a dynamic reconfiguration protocol that permits reassignment of network addresses to the front layer machines.

Abstract: A method for the synthesis of multi-level combinational circuits with cyclic topologies. The techniques, applicable in logic synthesis, and in particular in the structuring phase of logic synthesis, optimize a multi-level description, introducing feedback and potentially optimizing the network.

Abstract: A scalable, distributed, highly available, load balancing server system having multiple machines is provided that functions as a front server layer between a network (such as the Internet) and a back-end server layer having multiple machines functioning as Web file servers, FTP servers, or other application servers. The front layer machines comprise a server cluster that performs fail-over and dynamic load balancing for both server layers. The operation of the servers on both layers is monitored, and when a server failure at either layer is detected, the system automatically shifts network traffic from the failed machine to one or more operational machines, reconfiguring front-layer servers as needed without interrupting operation of the server system. The server system automatically accommodates additional machines in the server cluster, without service interruption. The system operates with a dynamic reconfiguration protocol that permits reassignment of network addresses to the front layer machines.

Abstract: A system for continuous monitoring and autonomous detection of patterns in the main memory subsystem of a computer system. The invention can be embodied as an extension to existing memory scrubbing hardware to permit stored code pattern analysis and identification during the autonomous transparent memory scrubbing process. A library of stored target signatures is provided to which code signatures are compared during analysis. Code signatures may be derived directly from the memory subsystem data pattern or may be indirectly and more efficiently derived from the error correction code (ECC) string associated with the stored data pattern. This invention is directly applicable to computer virus detection and neutralization systems.

Abstract: Disclosed is is a switch-based network interconnection which uses intelligent switching apparatus devices for improving the performance and connection establishing capability of multi-stage switching networks. The invention method is particularly effective In asynchronous circuit-switched networks. The most important feature of the invention methodology is the an increasing probability for the success of making a connection through all the stages of a multi-satge network. As a connection progresses through a multi-stage network, it must win successive stages of the network, one at a time, until it has made its way from on side of the network to the other and established the commanded source-to-destination connection. The uniqueness in the present invention is that as the connection at each stage of the network is established, looking forward to the next stage, the probability will be greater of establishing the next connection without encountering blocking than it was for the present stage.

Abstract: The multi-stage interconnection network of the present invention includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

Abstract: Disclosed is a method and system for performing a partial-sum query in a database in which the data is represented as a multi-dimensional data cube. The data cube is partitioned into multi-dimensional blocks. One or more covering codes are then selected for each block, and a group of partial-sums is computed for each block based on its covering codes. At query time, the query result is generated by combining the partial-sums for those blocks that intersect with the query subset. To improve the query response time and reduce system storage requirements, the covering codes are preferably augmented as single-weight extended covering codes or composition-extended covering codes. Also, a second partial-sum may also be computed for each block to efficiently find its partial sum, based on the block's first partial-sums and the bit-position differences between selected codewords for the block and bit strings representing the cell indexes of the blocks intersecting with the query subset.

Abstract: The present invention addresses the limitations of prior art ALLNODE switches by including dual priority, adaptive, path seeking, and flash-flood functionalities in a single ALLNODE switch. The switch of the present invention further includes a selection device responsive to a selection signal for enabling the selection of the mode of switch operation from any one of the foregoing functionalities. The selection signal is applied to the switch in a number of different ways including: the transmission of a command over the data path interface to the switch; the transmission of a command over special purpose serial or parallel control lines; or via hardwiring. Thus, the selection of functionality for the switch is capable of being made in either a dynamic or static fashion. The present invention further comprises two new high performance networks utilizing the selectable function ALLNODE switch.

Abstract: A method and apparatus for encoding and detecting data which can be represented in a physical array of modules recorded on a medium. Information is encoded in "image-blocks". An image-block comprises a plurality of "sub-blocks". Sub-blocks comprise a plurality of "modules". A module is the smallest unit of information within the image-block. Discrete contiguous portions of each sub-block of an image-block taken together are encoded into an outer codeword. A plurality of these outer codewords are generated and recorded across each sub-block. A portion of the information that is to be recorded within each sub-block is encoded in a plurality of inner error detection and correction codewords, each preferably stored entirely within one corresponding sub-block. Accordingly, small scattered random errors can be corrected locally by using information entirely contained within the sub-block.