Abstract: A multi-stage interconnection network includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

Abstract: An error checking method and apparatus for appending a variable number of redundancy coding information at the end of each data message or packet transmitted over a multi-stage network for the purpose of protecting the data by using an error detecting code. The amount of additional redundancy coding information implemented is variable and increases with the size of the data message or packet to provide a consistent level of protection.

Abstract: The data contents of up to two concurrently failed or erased DASDs can be reconstituted where the data is distributed across M DASDs as an (M-1)*M block array and where (1) the (M-1)st DASD contains the simple parity taken over each of the array diagonals in diagonal major order in the same mode (odd/even) as that exhibited by the major diagonal of the array and (2) where the M-th DASD contains the simple even parity over each of the rows in row major order. Relatedly, short write updates require fewer operations for data blocks located off the major data array diagonal.

Abstract: A method for routing multiple message packets to their respective destinations on a parallel system is disclosed which takes into account the value of the communication start-up time and the transmission time For the specific parallel system. The preferred embodiment involves first selecting a base using the parameters of communication start-up and transmission time and then for each datablock, subtracting the node address from the destination address of the datablock using the modulo-n subtractions to Form a relative offset and representing the relative offset in the pre-selected base before sending the datablocks to their destination nodes in phases, each phase involving scanning the individual i-th digits of the relative offset value and packing those datablocks with identical i-th digits of the relative offset together.

Abstract: A multi-stage circuit switched network for improving connection establishment using intelligent switching devices. As a transmission makes its way through the network stages, the probability of connecting to a destination increases, i.e., the chance of encountering a blocked device output is decreased. This is opposite of most traditional networks, whose probability for success diminishes with every stage in the connection sequence.

Abstract: A method is disclosed, for use with a multiprocessing hardware mesh architecture including nodes and a network of interconnections between the nodes, for defining and implementing a target logical mesh architecture utilizing a given subset of the nodes and the interconnections of the hardware architecture. Typically, the hardware mesh architecture includes redundant nodes and interconnections, sot hat the target logical mesh architecture may be defined from the hardware architecture several different ways. As a consequence, the target logical mesh architecture may be defined even in the presence of faulty nodes or interconnections in the hardware architecture. Frequently, the logical mesh is defined in terms of some regular pattern of interconnections.

Abstract: A method is disclosed for recovery from synchronization errors caused by deletions and/or insertions of symbols in the presence of errors that alter the symbols in any code constrained binary record. The method initially divides the sequence of data into equal size blocks before appending a binary sync sequence at the end of each block not encountered in the block. Then, the blocks are resynchronized by first determining the size of any symbol insertions and/or deletions that have occurred. Then, scanning for the sync sequence starting at the presumed end of the data field of the current block so as to determine the offset of the sync sequence with respect to that specific location. After this location of the insertions and/or deletions has been determined, a corresponding number of symbols can be added or deleted from the middle of the block according to the offset determined by the present method.

Abstract: A method and apparatus for encoding and decoding a (t.sub.1,t.sub.2)-skew-tolerant (ST) (t.sub.1 +s.sub.1,t.sub.2 +s.sub.2)-skew-detecting (SD) code, and for correcting and detecting skewed transitions in a parallel asynchronous communication system without acknowledgement, where t.sub.1, t.sub.2, s.sub.1, and s.sub.2 are selectable nonnegative integers. Even though transitions sent at the same time in parallel channels may arrive at different times, a limited degree of variation in transmission speeds is permitted between channels.Assume t.sub.1 is the maximum correctable number and t.sub.1 +s.sub.1 the maximum detectable number of transitions that can be missing from a first transmitted codeword when the first transition arrives from a second transmitted codeword, and t.sub.2 is the maximum correctable number and t.sub.2 +s.sub.2 the maximum detectable number of transitions from the second codeword that can arrive before the last transition of the first codeword arrives.

Abstract: The logical comparison and arithmetic addition functions are optimally constructed in depth-2 threshold logic circuits employing majority elements arranged into structures corresponding to sparse delta polynomials. A delta polynomial is a polynomial having a relatively large value for a particular set of variable values and having a relatively small value for all other sets of variable values. A delta polynomial can be constructed through a column-by-column consideration of an error-correcting code generator matrix. The sparseness of a delta polynomial constructed in this manner means that the delta polynomial expression for implementing a threshold logic circuig which combines n-bit numbers contains no more than n.sup.c terms. A further benefit of such a delta polynomial is the low values of its coefficients.

Abstract: Disclosed is a method and apparatus for improving the performance and connection establishing capability of multi-stage switching networks by providing additional intelligent features in the individual switching apparatus devices at each stage of the network. The invention method is particularly effective in asynchronous circuit-switched networks. The most important feature to be added is adaptivity of the switching apparatus; where adaptivity means the ability of each switching element to determine for itself which of several optional alternate paths to try at each stage of the network based on availability. This is a better approach because it brings the decision directly to the switching apparatus involved, which has the data required to make an intelligent path selection decision to circumvent blocking in the multi-stage network.

Abstract: An unordered error correcting code is constructed by an encoding method and apparatus that accepts k bits of information and is capable of providing unordered ECC codewords. All pairs of these codewords are at least a distance d apart, where d.gtoreq.(2t+1) and t is the maximum number of errors correctable by the code. The k bits of information are encoded with an ECC encoding algorithm to produce ECC codewords that are at least distance d apart. The least number of tail bits required to produce the unordered ECC codewords is appended to each of the ECC codewords. The tail bits for each codeword are constructed by dividing its weight by d for determining the integer part of the resulting quotient, generating a binary representation of the value of its integer part, and complementing said binary representation. A noisy received version of the ECC codeword with tail bits truncated is decoded and a preselected error correcting algorithm is applied to correct t.sub.

Abstract: A method and apparatus are presented for tolerating up to k faults in d-dimensional mesh architectures based on the approach of adding spare components (nodes) and extra links (edges) to a given target mesh where exactly k spare nodes are added and the number of links per node (degree of the mesh) is kept to a minimum. The resulting architecture can be reconfigured, without the use of switches, as an operable target mesh in the presence of up to k faults. According to one aspect of the invention, given a d-dimensional mesh architecture M having N=n.sub.1 .times.n.sub.2 x . . . x n.sub.d nodes, the fault tolerant mesh can be represented by a circulant graph having exactly N+k nodes. This graph has the property that given any set of k or fewer faulty nodes, the remaining graph, after the performance of a predetermined node renaming process, is guaranteed to contain as a subgraph the graph corresponding to target mesh M so long as d.gtoreq.2 and n.sub.d .gtoreq.3.

Abstract: An algorithm for a (t.sub.1, t.sub.2)-tolerant code, and a method and apparatus for decoding same, for tolerating and detecting skewed transitions in a parallel asynchronous communication system without acknowledgement. Transitions sent at the same time in a parallel channel may arrive at different times, but the algorithm permits a limited degree of variation in transmission speeds between channels. Errors will be corrected and transmissions will be continuous as long as the values of t.sub.1 or t.sub.2 for the algorithm, as preselected by the user, are not exceeded. If they are exceeded, a desired control operation will generally be initiated. t.sub.1 is the maximum number of transmissions that may be missing from a first transmitted codeword when a transmission arrives from a second transmitted codeword, and t.sub.2 is the maximum number of transitions from the second codeword that may arrive before all transitions of the first codeword arrive.

Abstract: An algorithm for a (t.sub.1,t.sub.2)-detecting code, and a method and apparatus for decoding same, for detecting skewed transitions in a parallel asynchronous communication system without acknowledgement. Transitions sent at the same time in a parallel channel may arrive at different times, but the algorithm permits a limited degree of variation in transmission speeds between channels. A desired control operation will be initiated whenever a skewed transition occurs. The code will detect up to t.sub.1 or t.sub.2 skewed transitions. The values of t.sub.1 or t.sub.2 for the algorithm are preselected by the user. t.sub.1 is the maximum number of transitions that may be missing from a first transmitted codeword when a transition arrives from a second transmitted codeword, and t.sub.2 is the maximum number of transitions from the second codeword that may arrive before all transitions of the first codeword arrive.

Abstract: A method and apparatus are presented for tolerating up to k faults in a d-dimensional mesh architecture based on the approach of adding spare components (nodes) and extra links (edges) to a given target mesh where m spare nodes (m.gtoreq.k) are added and the maximum number of links per node (degree of the mesh) is kept small. The resulting architecture can be reconfigured, without the use of switches, as an operable target mesh in the presence of up to k faults, regardless of their distribution. According to one aspect of the invention, given a d-dimensional mesh architecture having N=n.sub.1 .times.n.sub.2 .times.. . . .times.n.sub.d nodes, the fault-tolerant mesh can be represented by a diagonal or circulant graph having N+m-k nodes, where m.gtoreq.k. This graph has the property that given any set of k or fewer faulty nodes, the remaining graph, after the performance of a pre-determined node renaming process, is guaranteed to contain as a subgraph the graph corresponding to the target mesh M so long as d.