Patents by Inventor Jei-Ming Chen
Jei-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140256115Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Chien Liu, Chia-Lung Chang, Jei-Ming Chen, Jui-Min Lee, Yuh-Min Lin
-
Publication number: 20140213034Abstract: A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material.Type: ApplicationFiled: January 29, 2013Publication date: July 31, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Lung Chang, Chih-Chien Liu, Jei-Ming Chen, Wen-Yi Teng, Jui-Min Lee, Keng-Jen Lin, Chin-Fu Lin
-
Publication number: 20140199836Abstract: A method for forming an interlevel dielectric (ILD) layer includes the following steps. A MOS transistor on a substrate is provided. A first undoped oxide layer is deposited to cover the substrate and the MOS transistor. The first undoped oxide layer is planarized. A phosphorus containing oxide layer is deposited on the first undoped oxide layer. A second undoped oxide layer is deposited on the phosphorus containing oxide layer.Type: ApplicationFiled: January 13, 2013Publication date: July 17, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jei-Ming Chen, Yuh-Min Lin
-
Patent number: 8772904Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.Type: GrantFiled: June 13, 2012Date of Patent: July 8, 2014Assignee: United Microelectronics Corp.Inventors: Chih-Chien Liu, Chia-Lung Chang, Jei-Ming Chen, Jui-Min Lee, Yuh-Min Lin
-
Publication number: 20140134824Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jei-Ming Chen, Wen-Yi Teng, Chia-Lung Chang, Chih-Chien Liu
-
Patent number: 8709901Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.Type: GrantFiled: April 17, 2013Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Chia-Lung Chang, Wu-Sian Sie, Jei-Ming Chen, Wen-Yi Teng, Chih-Chien Liu, Jui-Min Lee, Chih-Hsun Lin
-
Patent number: 8692332Abstract: A structure of a strained-silicon transistor includes a PMOS disposed on a substrate, a silicon nitride layer positioned on the PMOS, and a compressive stress film disposed on the silicon nitride layer, wherein the silicon nitride has a stress between ?0.1 Gpa and ?3.2 Gpa, and the stress of the silicon nitride is smaller than the stress of the compressive stress layer.Type: GrantFiled: January 14, 2010Date of Patent: April 8, 2014Assignee: United Microelectronics Corp.Inventors: Jei-Ming Chen, Hsiu-Lien Liao, Yu-Tuan Tsai, Teng-Chun Tsai
-
Publication number: 20140091395Abstract: A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a lower tensile stress than the second tensile stress layer.Type: ApplicationFiled: October 1, 2012Publication date: April 3, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Chien Liu, Tzu-Chin Wu, Yu-Shu Lin, Jei-Ming Chen, Wen-Yi Teng
-
Patent number: 8674452Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first gate structure disposed on the first region, wherein the first gate structure comprises a first high-k dielectric layer, a first work function metal layer, and a first metal layer disposed between the first high-k dielectric layer and the first work function metal layer; and a second gate structure disposed on the second region, wherein the second gate structure comprises a second high-k dielectric layer, a second work function metal layer, and a second metal layer disposed between the second high-k dielectric layer and the second work function metal layer, wherein the thickness of the second metal layer is lower than the thickness of the first metal layer.Type: GrantFiled: June 24, 2011Date of Patent: March 18, 2014Assignee: United Microelectronics Corp.Inventors: Chin-Cheng Chien, Tzung-Ying Lee, Tsuo-Wen Lu, Shu-Yen Chan, Jei-Ming Chen, Yu-Min Lin, Chun-Wei Hsu
-
Publication number: 20140042501Abstract: A MOS transistor includes a gate structure and a spacer. The gate structure is located on a substrate. The spacer is located on the substrate beside the gate structure, and the spacer includes an L-shaped inner spacer and an outer spacer, wherein the outer spacer is located on the L-shaped inner spacer, and the two ends of the L-shaped inner spacer protrude from the outer spacer. Moreover, the present invention also provides a MOS transistor process for forming the MOS transistor.Type: ApplicationFiled: August 10, 2012Publication date: February 13, 2014Inventors: Jei-Ming Chen, Chih-Chien Liu, Yu-Shu Lin, Tzu-Chin Wu
-
Publication number: 20140038374Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.Type: ApplicationFiled: October 22, 2013Publication date: February 6, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Wei Chen, Teng-Chun Tsai, Chien-Chung Huang, Jei-Ming Chen, Tsai-Fu Hsiao
-
Publication number: 20140035070Abstract: A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k dielectric layer, and a work function layer disposed on and contacted with the barrier layer. The MOS transistor further includes a dielectric material spacer. The dielectric material spacer is disposed on the barrier layer of each of the first gate structure and the second gate structure and surrounding the work function layer of each of the first gate structure and the second gate structure.Type: ApplicationFiled: October 4, 2013Publication date: February 6, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Tsuo-Wen Lu, Tzung-Ying Lee, Jei-Ming Chen, Chun-Wei Hsu, Yu-Min Lin, Chia-Lung Chang, Chin-Cheng Chien, Shu-Yen Chan
-
Publication number: 20130334650Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Inventors: Chih-Chien Liu, Chia-Lung Chang, Jei-Ming Chen, Jui-Min Lee, Yuh-Min Lin
-
Patent number: 8580625Abstract: A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.Type: GrantFiled: July 22, 2011Date of Patent: November 12, 2013Inventors: Tsuo-Wen Lu, Tzung-Ying Lee, Jei-Ming Chen, Chun-Wei Hsu, Yu-Min Lin, Chia-Lung Chang, Chin-Cheng Chien, Shu-Yen Chan
-
Patent number: 8536038Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.Type: GrantFiled: June 21, 2011Date of Patent: September 17, 2013Assignee: United Microelectronics Corp.Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Wen-Yi Teng, Tsuo-Wen Lu, Chih-Chung Chen, Ying-Wei Yen, Yu-Min Lin, Chin-Cheng Chien, Jei-Ming Chen, Chun-Wei Hsu, Chia-Lung Chang, Yi-Ching Wu, Shu-Yen Chan
-
Publication number: 20130020657Abstract: A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.Type: ApplicationFiled: July 22, 2011Publication date: January 24, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tsuo-Wen LU, Tzung-Ying Lee, Jei-Ming Chen, Chun-Wei Hsu, Yu-Min Lin, Chia-Lung Chang, Chin-Cheng Chien, Shu-Yen Chan
-
Publication number: 20120329261Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.Type: ApplicationFiled: June 21, 2011Publication date: December 27, 2012Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Wen-Yi Teng, Tsuo-Wen Lu, Chih-Chung Chen, Ying-Wei Yen, Yu-Min Lin, Chin-Cheng Chien, Jei-Ming Chen, Chun-Wei Hsu, Chia-Lung Chang, Yi-Ching Wu, Shu-Yen Chan
-
Publication number: 20120326238Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region thereon; forming a high-k dielectric layer, a barrier layer, and a first metal layer on the substrate; removing the first metal layer of the second region; forming a polysilicon layer to cover the first metal layer of the first region and the barrier layer of the second region; patterning the polysilicon layer, the first metal layer, the barrier layer, and the high-k dielectric layer to form a first gate structure and a second gate structure in the first region and the second region; and forming a source/drain in the substrate adjacent to two sides of the first gate structure and the second gate structure.Type: ApplicationFiled: June 24, 2011Publication date: December 27, 2012Inventors: Chin-Cheng Chien, Tzung-Ying Lee, Tsuo-Wen Lu, Shu-Yen Chan, Jei-Ming Chen, Yu-Min Lin, Chun-Wei Hsu
-
Publication number: 20120071004Abstract: A stress-adjusting method for use in a manufacturing system of a MOS device is provided. At first, a first stress layer is formed onto a substrate wherein at least two MOSFETs are previously formed on the substrate. The first stress layer overlies an inter-gate region between two adjacent gate regions of the MOSFETs and overlies the two adjacent gate regions. Then, the first stress layer in the inter-gate region is thinned. A second stress layer is further formed onto the substrate to overlie the thinned first stress layer in the inter-gate region to provide the resulting MOS device with satisfactory stress.Type: ApplicationFiled: September 17, 2010Publication date: March 22, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jei-Ming CHEN, Szu-Hao LAI
-
Publication number: 20110169095Abstract: A structure of a strained-silicon transistor includes a PMOS disposed on a substrate, a silicon nitride layer positioned on the PMOS, and a compressive stress film disposed on the silicon nitride layer, wherein the silicon nitride has a stress between ?0.1 Gpa and ?3.2 Gpa, and the stress of the silicon nitride is smaller than the stress of the compressive stress layer.Type: ApplicationFiled: January 14, 2010Publication date: July 14, 2011Inventors: Jei-Ming Chen, Hsiu-Lien Liao, Yu-Tuan Tsai, Teng-Chun Tsai