Patents by Inventor Jei-Ming Chen

Jei-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070085210
    Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.
    Type: Application
    Filed: January 26, 2006
    Publication date: April 19, 2007
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Chun-Chieh Huang, Jei-Ming Chen, Shu-Jen Sung
  • Publication number: 20070077751
    Abstract: A method of restoring a low-k material is described, applied to a substrate with a low-k material thereon, wherein the substrate has been subject to a previous process that raised the k-value of the low-k material. The method includes performing a plasma treatment to the low-k material to decrease the k-value thereof.
    Type: Application
    Filed: October 3, 2005
    Publication date: April 5, 2007
    Inventors: Mei-Ling Chen, Jei-Ming Chen, Kuo-Chih Lai, Wen-Chieh Su
  • Publication number: 20060281299
    Abstract: A dielectric layer overlying a substrate is prepared. A damascene opening is etched into the dielectric layer. The damascene opening is filled with copper or copper alloy. A surface of the copper or copper alloy is treated with hydrogen-containing plasma such as H2 or NH3 plasma. The treated surface of the copper or copper alloy then reacts with trimethylsilane or tertramethylsilane under plasma enhanced chemical vapor deposition (PECVD) conditions. Subsequently, by PECVD, a silicon carbide layer is in-situ deposited on the copper or copper alloy.
    Type: Application
    Filed: August 3, 2006
    Publication date: December 14, 2006
    Inventors: Jei-Ming Chen, Chin-Hsiang Lin, Chih-Chien Liu, Kuo-Chih Lai
  • Publication number: 20060199367
    Abstract: A manufacturing method of interconnect is provided. A dielectric layer is provided. A metal layer is formed in the dielectric layer. A fluorine-containing barrier layer is formed on the dielectric layer and covers the metal layer. The fluorine-containing barrier layer is formed by using chemical deposition method and introducing fluorine to the film in-situ.
    Type: Application
    Filed: December 7, 2005
    Publication date: September 7, 2006
    Inventors: Jim-Jey Huang, Chih-Chien Liu, Feng-Yu Hsu, Jei-Ming Chen, Kuo-Chih Lai
  • Publication number: 20060040490
    Abstract: A dielectric layer overlying a substrate is prepared. A damascene opening is etched into the dielectric layer. The damascene opening is filled with copper or copper alloy. A surface of the copper or copper alloy is treated with hydrogen-containing plasma such as H2 or NH3 plasma. The treated surface of the copper or copper alloy then reacts with trimethylsilane or tertramethylsilane under plasma enhanced chemical vapor deposition (PECVD) conditions. Subsequently, by PECVD, a silicon carbide layer is in-situ deposited on the copper or copper alloy.
    Type: Application
    Filed: August 18, 2004
    Publication date: February 23, 2006
    Inventors: Jei-Ming Chen, Chin-Hsiang Lin, Chih-Chien Liu, Kuo-Chih Lai
  • Patent number: 6960522
    Abstract: A method for making a damascene interconnect structure with a bi-layer capping film is provided. The damascene interconnect structure comprises a semiconductor layer and a dielectric layer disposed on the semiconductor layer. The dielectric layer has a main surface and at least one damascened recess provided on the main surface. A copper wire is embedded in the damascened recess. The copper wire has a chemical mechanical polished upper surface, which is substantially co-planar with the main surface of the dielectric layer. After polishing the upper surface of the copper wire, the upper surface is pre-treated and reduced in a conductive plasma environment at a temperature of below 300° C. A bi-layer capping film is thereafter disposed on the upper surface of the copper wire. The bi-layer capping film consists of a lower HDPCVD silicon nitride layer and an upper doped silicon carbide layer.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: November 1, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Jei-Ming Chen, Yi-Fang Chiang, Chih-Chien Liu
  • Patent number: 6873057
    Abstract: A damascene interconnect structure with a bi-layer capping film is provided. The damascene interconnect structure comprises a semiconductor layer and a dielectric layer disposed on the semiconductor layer. The dielectric layer has a main surface and at least one damascened recess provided on the main surface. A copper wire is embedded in the damascened recess. The copper wire has a chemical mechanical polished upper surface, which is substantially co-planar with the main surface of the dielectric layer. After polishing the upper surface of the copper wire, the upper surface is pre-treated and reduced in a conductive plasma environment at a temperature of below 300° C. A bi-layer capping film is thereafter disposed on the upper surface of the copper wire. The bi-layer capping film consists of a lower HDPCVD silicon nitride layer and an upper doped silicon carbide layer.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: March 29, 2005
    Assignee: United Microelectrtonics Corp.
    Inventors: Jei-Ming Chen, Yi-Fang Chiang, Chih-Chien Liu
  • Publication number: 20040166674
    Abstract: A method for making a damascene interconnect structure with a bi-layer capping film is provided. The damascene interconnect structure comprises a semiconductor layer and a dielectric layer disposed on the semiconductor layer. The dielectric layer has a main surface and at least one damascened recess provided on the main surface. A copper wire is embedded in the damascened recess. The copper wire has a chemical mechanical polished upper surface, which is substantially co-planar with the main surface of the dielectric layer. After polishing the upper surface of the copper wire, the upper surface is pre-treated and reduced in a conductive plasma environment at a temperature of below 300° C. A bi-layer capping film is thereafter disposed on the upper surface of the copper wire. The bi-layer capping film consists of a lower HDPCVD silicon nitride layer and an upper doped silicon carbide layer.
    Type: Application
    Filed: March 2, 2004
    Publication date: August 26, 2004
    Inventors: Jei-Ming Chen, Yi-Fang Chiang, Chih-Chien Liu
  • Publication number: 20040161924
    Abstract: A damascene interconnect structure with a bi-layer capping film is provided. The damascene interconnect structure comprises a semiconductor layer and a dielectric layer disposed on the semiconductor layer. The dielectric layer has a main surface and at least one damascened recess provided on the main surface. A copper wire is embedded in the damascened recess. The copper wire has a chemical mechanical polished upper surface, which is substantially co-planar with the main surface of the dielectric layer. After polishing the upper surface of the copper wire, the upper surface is pre-treated and reduced in a conductive plasma environment at a temperature of below 300 ° C. A bi-layer capping film is thereafter disposed on the upper surface of the copper wire. The bi-layer capping film consists of a lower HDPCVD silicon nitride layer and an upper doped silicon carbide layer.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 19, 2004
    Inventors: Jei-Ming Chen, Yi-Fang Chiang, Chih-Chien Liu