Abstract: A semiconductor read-only memory (ROM) device is provided. The particular semiconductor structure of this ROM device can reduce the parasitic capacitance between the bit lines and the word lines, such that the resistance-capacitance time constant of the memory cells can be reduced to thereby speed up the access time of the read operation to the memory cells. The binary data stored in each memory cell is dependent on whether one contact window is predefined to be formed in a thick insulating layer between the buried bit lines and the overlaying word lines. If the gate electrode of one memory cell is electrically connected to the associated word line via one contact window through the insulating layer, that memory cell is set to a permanently-ON state representing a first binary value; otherwise, that memory cell is set to a permanently-OFF state representing a second binary value.

Abstract: A semiconductor read-only memory (ROM) device is provided and includes an array of diode-based memory cells for storing binary data. Whether a memory cell of the ROM device is set to a permanently-ON or OFF state, depends upon whether the memory cell is formed with a junction diode, wherein the presence of a junction diode in the memory cell causes the memory cell to be set to a permanently-ON state. Formation of the junction diode includes the step of forming a plurality of parallel-spaced first diffusion regions of a semiconductor type, to serve as a plurality of bit lines. An insulating layer is then formed to cover the first diffusion regions. A plurality of contact windows are formed at predefined locations of the insulating layer where a first group of memory cells, set to a permanently-ON state, are formed. The unexposed portions of the first diffusion regions are associated with a second group of memory cells that are set to a permanently-OFF state.

Abstract: A manufacturing method and a structure for ROM component having a silicon controlled rectifier as the basic memory instead of a channel transistor in a conventional ROM, and using a formation of contact windows for coding a ROM instead of performing an ion implantation process. Also, since a silicon controlled rectifier occupies a smaller component surface area, the level of integration is correspondingly increased. Furthermore, due to interposition of an insulating layer between two bit lines, short circuiting between the adjacent bit lines is prevented. The component of this invention operates by applying a suitable voltage to the word line electrode and the bit line electrode respectively to select a particular memory unit, and as a result, a current will flow in a vertical direction through the memory unit, exit through the common electrode depending on the ON/OFF state of the memory, and be detected there.

Abstract: A method of manufacture for a multiple stage ROM unit capable of coding the multiple stages with a single coding implantation and a method of manufacturing the same.The ROM includes a semiconductor substrate covered by an insulating layer. A gate structure is provided above the insulating layer. A channel region is located on the substrate beneath the gate structure. Source/drain regions are disposed on the semiconductor substrate on each side of the channel region. A cap partially covers the top of the gate structure so as to divide the channel region therebelow into a first channel region and a second channel region such that multiple-level threshold voltages may be coded in the ROM.

Abstract: The present invention utilizes a first dielectric layer and a second dielectric layer overlying cell regions for storing a turned-off state or a turned-on state, respectively. The first dielectric layer is formed by local oxidation of polysilicon having a thickness greater than that of the second dielectric layer, such that the corresponding cell regions below the first dielectric layer have a threshold voltage greater than that of the second dielectric layer. Moreover, the formation of the first dielectric layer can lower the parasitic capacitance between the word lines and the bit lines as well as the substrate. Furthermore, the present invention does not require code-implantation. Thus, decreased breakdown voltage encountered in the conventional method can be avoided.

Abstract: A method of making a triple level ROM device includes forming at least first, second and third metallic oxide semiconductor (MOS) structures. Each MOS structure has a source terminal and a drain terminal located within a substrate, a channel located between the source and drain terminals, and a gate terminal structure located above the channel. The source and drain terminals serve as bit lines and the gate terminal serves as a word line. A dielectric layer and a cap layer are formed in sequence above the first, second and third MOS structures, thereby forming first, second and third memory cell units from the first, second and third MOS structures, respectively. A first coding process is performed, which includes forming a photoresist layer above the gate terminal structure of at least the first memory cell unit. Portions of the cap layer having no photoresist coverage are removed to form a cap above the first memory cell unit.

Abstract: A ROM (read-only memory) device of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells and a method for fabricating the same are provided. The method allows for better planarization of the wafer surface of the ROM device with increased gap fill capability. Further, the bit lines are formed by forming a substantially grid-like structure including a plurality of substantially parallel-spaced first portions oriented in a first direction and a plurality of substantially parallel-spaced second portions oriented in a second direction. The first portions serve as bit lines and the second portions serve as channels.

Abstract: A read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented. The diode-based structure also allows the packing density of the memory cells on the ROM device to be dependent on the line width of the polysilicon layers in the ROM device.

Abstract: A method of manufacture for a multiple stage ROM unit capable of coding the multiple stages with a single coding implantation and a method of manufacturing the same.The ROM includes a semiconductor substrate covered by an insulating layer. A gate structure is provided above the insulating layer. A channel region is located on the substrate beneath the gate structure. Source/drain regions are disposed on the semiconductor substrate on each side of the channel region. A cap partially covers the top of the gate structure so as to divide the channel region therebelow into a first channel region and a second channel region such that multiple-level threshold voltages may be coded in the ROM.

Abstract: A semiconductor read-only memory (ROM) device having a silicon-on-insulator (SOI) structure and a method for fabricating the same are provided. The SOI structure permits isolation of the source/drain regions from the underlying substrate, thereby preventing leakage current therebetween. The ROM device of the present invention is smaller than conventional ROM devices, and thus provides increased integration without generating leakage paths due to misalignment of the contact windows used to form metal interconnects. The ROM device includes a plurality of parallel gate regions and a grid-like polysilicon conductive layer. The grid-like structure includes a plurality of substantially parallel source/drain regions on both sides of the gate regions, and a plurality of substantially parallel channel regions crossing the source/drain regions and the gate regions at right angles. Select locations of the channel regions are impurity-doped, causing the associated memory cells to be set to a permanently-OFF state.

Abstract: A MOS device and method of fabricating the same, wherein the source/drain region has polysilicon trench structure which are formed by self-alignment using silicon oxide layers as masks. The source/drain regions extend to the field oxide layer and/or above the gate. Therefore, contacts can be formed on source/drain conductive regions above the field oxide layer.

Abstract: A method is provided for fabricating a ROM device for permanent storage of multi-level coded data therein. By the method, an array of MOSFET-based memory cells are first formed on a substrate, each being formed with an island-like gate region and a pair of source/drain regions. In accordance with customer specification, different groups of the memory cells are specified to respectively store a first, a second, a third, and a fourth value of the multi-level coded data. In the mask programming process, a first code-implantation process is performed to implant impurities into the respective channel regions of the second and fourth selected groups of the memory cells so as to vary the threshold voltage thereof. Then, an insulating layer is formed over the wafer, covering all of the memory cells. Next, a second code-implantation process is performed to form a plurality of contact windows in the insulating layer directly above the island-like gates of the first and second selected groups of the memory cells.

Abstract: A ROM (read-only memory) device of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells and a method for fabricating the same are provided. The method allows for better planarization of the wafer surface of the ROM device with increased gap fill capability. Further, the bit lines are formed by forming a substantially grid-like structure including a plurality of substantially parallel-spaced first portions oriented in a first direction and a plurality of substantially parallel-spaced second portions oriented in a second direction. The first portions serve as bit lines and the second portions serve as channels.

Abstract: A ROM structure and its method of manufacture using separate parallel trench bit lines for increasing memory component density as well as using a diode as the fundamental memory unit, each diode having a junction formed inside a bit line with a forward biased voltage of about 0.4 V and a reverse biased voltage dependent upon the doping condition in an N.sup.- region. At a junction between a word line and a bit line, either an ON state or an OFF state diode memory unit is created depending on whether a contact opening in the insulating layer for connection between the two is formed or not. When a definite operating voltage is applied to the word line, the stored information bit in the diode memory unit can be read off from the bit line by sensing a cut-off or a conducting current representing previous program coding of the diode memory unit.

Abstract: A ROM (read-only memory) device of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells and a method for fabricating the same are provided. The method allows for better planarization of the wafer surface of the ROM device with increased gap fill capability. Further, the bit lines are formed by forming a substantially grid-like structure including a plurality of substantially parallel-spaced first portions oriented in a first direction and a plurality of substantially parallel-spaced second portions oriented in a second direction. The first portions serve as bit lines and the second portions serve as channels.

Abstract: A multi-stage read only memory (ROM) device and a method for fabricating the same. The device includes a source/drain pole and a gate in a trench, wherein the gate intersects the source/drain pole in an angle to form a number of memory cells. The fabrication of the multi-stage ROM includes two encoding process. The first encoding process includes implantation of impurity ions in a portion of memory cells to adjust the threshold voltage, so that some of the memory cells have a first threshold voltage and the others have a second threshold voltage. The second encoding process includes forming a spacer on the opposite side-walls of the gate trench of a portion of the memory cells, so that some of the memory cells have a first effective channel width and the others have a second effective channel width. As a result, the memory cells of a ROM are of four types with different combinations of threshold voltages and effective channel widths.

Abstract: A high-voltage MOS (metal-oxide semiconductor) device and a method for fabricating the same is provided. The high-voltage MOS device features the forming of trench-type source/drain structure in substitute of conventional highly doped structure formed by implantation. The improved structure allows the source/drain regions to occupy a small area for layout on the chip. In addition, the forming of the trench-type source/drain structure in N-wells allows an increased current path from the source/drain regions to drift regions, meaning that the conductive path for the current is not limited to only the junction between the source/drain regions and the drift regions as in conventional structures. Moreover, since the trench-type source/drain structure extends upwards from the inside of N-wells to above the surface of isolation layers, metal contact windows can be formed above the isolation layers, thus preventing the occurrence of leakage current.

Abstract: A method is provided for fabricating a read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented.

Abstract: A fabricating method for a ROM device uses the Shockly diode as a memory cell in the ROM device. In the present invention, the current of the memory cell is larger than that of a convention one. In the conventional ROM device, the code is programmed by making use of the channel transistor as the memory cell and implanting. In the present invention, the code is programmed by defining contact windows of the ROM device to prevent the ROM device from the shortcomings of limited current. In addition, the memory cells of the ROM device of a Shockly diode are isolated by an insulating layer, resulting in a smaller area for the device and improved integrity.

Abstract: A ROM device of the type including an array of diode-type memory cells and a method for fabricating the same are provided. The bit lines of this ROM device are a plurality of diffusion regions formed in an alternate manner on the bottom of a plurality of parallel-spaced trenches and on the top of the solid portions between these trenches. This particular arrangement of the bit lines allows for an increased integration of the diode-type memory cells on a limited wafer surface without having to reduce the feature size of the semiconductor components of the ROM device. The diode-type memory cells that are set to a permanently-ON state involve a P-N junction diode being formed therein, wherein the P-N junction diode is electrically connected via a contact window in an insulating layer to the associated one of the overlaying word lines. Other memory cells that are set to a permanently-OFF state are formed with no P-N junction diode therein.