Abstract: A new semiconductor structure for a ROM device and a method for fabricating the same are provided. The ROM device includes a plurality of trench-type source/drain regions which serve as a plurality of bit lines for the ROM device. By this method, the conventional step of using ion implantation to form the bit lines can be eliminated. Further, an insulating layer is formed between the source/drain regions and the underlying a substrate such that the leakage current in the junction between the source/drain regions and the substrate can be minimized. The ON/OFF state of each of the MOSFET memory cells of the ROM device is dependent on whether the associated channel region comes into lateral contact with the neighboring source/drain regions through a mask removed portion of the insulating layer.

Abstract: A read-only memory (ROM) and method for manufacturing a ROM having trench-type gate regions and source/drain regions, wherein the trench-type gate regions are provides in a substrate. The ROM further includes an insulating layer for isolating the substrate from the source/drain regions so to prevent current leakage between the source/drain regions and the substrate and to reduce area required by components of the ROM, thereby increasing component integration. The ROM also comprises a checkerboard conductive layer having a plurality of parallel source/drain regions a plurality of parallel channel regions connected to the plurality of parallel source/drain regions, wherein the plurality of parallel source/drain regions and the plurality of parallel channel regions cross each other at right angle, while the source/drain regions and the trench-type gate regions are approximately parallel to each other.

Abstract: A method for fabricating a semiconductor read-only memory (ROM) device of the type including a plurality of diode-type memory cells is provided. The ROM device is based on a silicon-on-insulation (SOI) structure in which all of the memory cells of the ROM device are formed in an insulating layer over a silicon substrate. The SOI structure allows for the prevention of leakage current between neighboring bit lines. The memory cells of the ROM device are each based on a P-N junction diode, which allows for a higher integration of the memory cells on a single chip than the use of MOSFET-based memory cells. The coding process is also easier to conduct.

Abstract: A multi-stage read only memory (ROM) device and a method for fabricating the same. The device includes a source/drain pole and a gate in a trench, wherein the gate intersects the source/drain pole in an angle to form a number of memory cells. The fabrication of the multi-stage ROM includes two encoding process. The first encoding process includes implantation of impurity ions in a portion of memory cells to adjust the threshold voltage, so that some of the memory cells have a first threshold voltage and the others have a second threshold voltage. The second encoding process includes forming a spacer on the opposite side-walls of the gate trench of a portion of the memory cells, so that some of the memory cells have a first effective channel width and the others have a second effective channel width. As a result, the memory cells of a ROM are of four types with different combinations of threshold voltages and effective channel widths.

Abstract: A multi-stage read only memory (ROM) device and a method for fabricating the same. The device includes a source/drain pole and a gate in a trench, wherein the gate intersects the source/drain pole at an angle to form a number of memory cells. The fabrication of the multi-stage ROM includes two encoding processes. The first encoding process includes implantation of impurity ions in a portion of memory cells to adjust the threshold voltage, so that some of the memory cells have a first threshold voltage and the others have a second threshold voltage. The second encoding process includes forming a number of dielectric remainders at the bottom of the gate trench of a portion of the memory cells, so that some of the memory cells have a first effective channel width and the others have a second effective channel width. As a result, the memory cells of a ROM are of four types with different combinations of threshold voltages and effective channel widths.

Abstract: A read-only memory (ROM) and method for manufacturing a ROM having trench-type gate regions and source/drain regions, wherein the trench-type gate regions are provided in a substrate. The ROM further includes an insulating layer for isolating the substrate from the source/drain regions so to prevent current leakage between the source/drain regions and the substrate and to reduce area required by components of the ROM, thereby increasing component integration. The ROM also comprises a checkerboard conductive layer having a plurality of parallel source/drain regions a plurality of parallel channel regions connected to the plurality of parallel source/drain regions, wherein the plurality of parallel source/drain regions and the plurality of parallel channel regions cross each other at right angle, while the source/drain regions and the trench-type gate regions are approximately parallel to each other.

Abstract: A NAND-structure and amorphous-silicon based ROM device is provided. This ROM device is of the type including an array of MOSFET memory cells that are constructed based on a silicon-on-insulator (SOI) structure, so as to isolate the source/drain regions from the underlying substrate to prevent the occurrence of leakage current therebetween. Further, the SOI structure prevents occurrence of breakdown at the diode junction between the source/drain regions and the substrate for increased operating voltage. In this ROM device, the source/drain regions for the MOSFET memory cells are formed from the intrinsic amorphous-silicon, instead of highly-doped polysilicon, so that the fabrication process for the ROM device is significantly simplified.

Abstract: A new semiconductor structure for a ROM device and a method for fabricating the same are provided. The ROM device includes a plurality of trench-type source/drain regions which serve as a plurality of bit lines for the ROM device. By this method, the conventional step of using ion implantation to form the bit lines can be eliminated. Further, an insulating layer is formed between the source/drain regions and the underlying substrate such that the leakage current in the junction between the source/drain regions and the substrate can be minimized. The ON/OFF state of each of the MOSFET memory cells of the ROM device is dependent on whether the associated channel region comes into lateral contact with the neighboring source/drain regions through a mask removed portion of the insulating layer.

Abstract: A multi-stage read only memory (ROM) device and a method for fabricating the same. The device includes a source/drain pole and a gate in a trench, wherein the gate intersects the source/drain pole at an angle to form a number of memory cells. The fabrication of the multi-stage ROM includes two encoding processes. The first encoding process includes implantation of impurity ions in a portion of memory cells to adjust the threshold voltage, so that some of the memory cells have a first threshold voltage and the others have a second threshold voltage. The second encoding process includes forming a number of dielectric remainders at the bottom of the gate trench of a portion of the memory cells, so that some of the memory cells have a first effective channel width and the others have a second effective channel width. As a result, the memory cells of a ROM are of four types with different combinations of threshold voltages and effective channel widths.

Abstract: A ROM device using a Shockly diode uses the Shockly diode as a memory cell in the ROM device. In the present invention, the current of the memory cell is larger than that of a convention one. In the conventional ROM device, the code is programmed by making use of the channel transistor as the memory cell and implanting. In the present invention, the code is programmed by defining contact windows of the ROM device to prevent the ROM device from the shortcomings of limited current. In addition, the memory cells of the ROM device of a Shockly diode are isolated by an insulating layer, resulting in a smaller area for the device and improved integrity.

Abstract: A manufacturing method and a structure for ROM component having a silicon controlled rectifier as the basic memory instead of a channel transistor in a conventional ROM, and using a formation of contact windows for coding a ROM instead of performing an ion implantation process. Also, since a silicon controlled rectifier occupies a smaller component surface area, the level of integration is correspondingly increased, and furthermore, because of the interposition of an insulating layer between two bit lines, short circuiting between the adjacent bit lines are prevented. The component of this invention operates by applying a suitable voltage to the word line electrode and the bit line electrode respectively to select a particular memory unit, and as a result, a current will flow in a vertical direction through the memory unit, exit through the common electrode depending on the ON/OFF state of the memory, and be detected there.

Abstract: A structure and manufacturing method for ROM suitable for high density component fabrication, mainly consisting of conducting diode memory cells having a forward bias voltage of about 0.4V located above a silicon substrate, and of non-conducting memory cells having only the bit lines embedded in the substrate, forming a memory unit for the storage and retrieval of data bits at the junction crossing between each word line and each bit line. When a suitable operating voltage is applied to a word line, a change of current flow detected in the selected bit line represents either the ON or OFF state of a memory unit and hence reflects the coded data bit.

Abstract: A diode-based ROM device and a method for fabricating the same are provided. The ROM device is of the type including an array of diode-based memory cells for permanent storage of binary-coded data therein. In the semiconductor structure of the ROM device, a plurality of insulator-filled trenches are formed for isolation of the diode-based memory cells. This feature allows the prevention of the punch-through effect when the ROM device is downsized. Further, the bit lines for the ROM device are formed with an increased junction depth such that the resistance of the bit lines can be reduced to allow an increase in the magnitude of the currents in the bit lines for easier detection and distinguishing of the binary state the currents represent.

Abstract: A multi-stage read only memory (ROM) device and a method for fabricating the same. The device includes a source/drain pole and a gate in a trench, wherein the gate intersects the source/drain pole at an angle to form a number of memory cells. The fabrication of the multi-stage ROM include two encoding processes. The first encoding process includes implantation of impurity ions in a portion of the memory cells to adjust the threshold voltage, so that some of the memory cells have a first threshold voltage and the others have a second threshold voltage. The second encoding process includes implanting the side-walls of the gate trench of a portion of the memory cells to form a number of stop diffusion regions, so that some of the memory cells have a first effective channel width and the others have a second effective channel width. As a result, the memory cells of a ROM are of four types with different combinations of threshold voltages and effective channel widths.

Abstract: A semiconductor read-only memory (ROM) device for permanent storage of multi-level coded data and a method of fabricating the same are provided. The ROM device is specifically devised for permanent storage of multi-level coded data that are represented by more than two logic states. The ROM device includes a semiconductor substrate formed an array of spaced major gate structures above the channel regions, and a plurality of minor gate structures formed between the major gate structures above the channel regions. Each of the major gate structures and one neighboring minor gate structure are in combination associated with one memory cell of the ROM device.

Abstract: The present invention discloses two kinds of ESD protection devices, an MOS transistor and an diode, and their method of fabrication. The MOS transistor is fabricated in a semiconductor substrate having a plurality of trenches formed therein at one side of its gate. One of the source/drain regions of the MOS transistor is formed in the substrate and disposed along the periphery of those trenches. The diode is fabricated in a semiconductor substrate having a plurality of trenches formed therein. A dope region is thereafter formed in the substrate and disposed along the periphery of those trenches. Accordingly, either the MOS transistor or diode has a vertically enlarged area along the trenches to effectively prevent ESD damage, but without consuming a great amount of horizontal chip area.

Abstract: The present invention utilizes a first dielectric layer and a second dielectric layer overlying cell regions for storing a turned-off state or a turned-on state, respectively. The first dielectric layer is formed by local oxidation of polysilicon having a thickness greater than that of the second dielectric layer, such that the corresponding cell regions below the first dielectric layer have a threshold voltage greater than that of the second dielectric layer. Moreover, the formation of the first dielectric layer can lower the parasitic capacitance between the word lines and the bit lines as well as the substrate. Furthermore, the present invention does not require code-implantation. Thus, decreased breakdown voltage encountered in the conventional method can be avoided.

Abstract: A semiconductor read-only memory (ROM) device is provided. The particular semiconductor structure of this ROM device can reduce the parasitic capacitance between the bit lines and the word lines, such that the resistance-capacitance time constant of the memory cells can be reduced to thereby speed up the access time to the memory cells. The binary data stored in each memory cell is dependent on whether a contact window is predefined to be formed in a thick insulating layer between the buried bit lines and the overlaying word lines. If the gate electrode of one memory cell is electrically connected to the associated word line via one contact window through the insulating layer, that memory cell is set to a permanently-ON state representing a first binary value; otherwise, that memory cell is set to a permanently-OFF state representing a second binary value. The threshold voltage of the permanently-ON memory cells is about in the range from 0.4 V to 0.7 V.

Abstract: A ROM device of the type including an array of diode-type memory cells and a method for fabricating the same are provided. The bit lines of this ROM device are a plurality of diffusion regions formed in an alternate manner on the bottom of a plurality of parallel-spaced trenches and on the top of the solid portions between these trenches. This particular arrangement of the bit lines allows for an increased integration of the diode-type memory cells on a limited wafer surface without having to reduce the feature size of the semiconductor components of the ROM device. The diode-type memory cells that are set to a permanently-ON state involve a P-N junction diode being formed therein, wherein the P-N junction diode is electrically connected via a contact window in an insulating layer to the associated one of the overlaying word lines. Other memory cells that are set to a permanently-OFF state are formed with no P-N junction diode therein.

Abstract: An improved SRAM cell having ultra-high density and methods for fabrication are described. Each SRAM cell, according to the present invention, has its own buried structure, including word lines (i.e., gate regions) and bit lines (i.e., source/drain regions), thus increasing the cell ratio of channel width of cell transistor to that of pass transistor to keep the data stored in the cell transistor more stable without increasing the area per cell. In addition, according to the present invention, the field isolation between active regions is not field oxide but blankly ion-implanted silicon substrate. Therefore, SRAM cells can be densely integrated due to the absence of bird's beak encroachment. Since the present invention has more planar topography than the prior art, it is easily adapted to the VLSI process, which is always restricted by the limit of resolution of photolithography, thus increasing the degree of integration.