Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.

Abstract: The present disclosure relates to an image sensor integrated chip (IC) structure. The image sensor IC structure includes a plurality of image sensing elements respectively disposed within a plurality of pixel regions of a pixel array within a substrate. An inter-level dielectric (ILD) structure is disposed on a surface of the substrate and surrounds one or more interconnects. A plurality of three-dimensional (3D) capacitors are arranged within respective ones of the plurality of pixel regions and are coupled to one of the plurality of image sensing elements by the one or more interconnects. The plurality of 3D capacitors include a base region extending in parallel to the surface of the substrate and one or more fingers extending outward from the base region along a direction perpendicular to the surface of the substrate.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure.

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device includes at least three metal plates that are spaced from one another. The MIM device further includes a plurality of capacitor insulator structures. Each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

Abstract: A pixel array that includes some pixels with high absorption (HA) structures and other pixels without HA structures exhibits increased dynamic range for near infrared (NIR) light. Additionally, the pixel array is a uniform array of photodiodes and thus does not exhibit current leakage that would have been caused by irregular isolation structures. Additionally, the pixel array may further a lateral overflow integration capacitor to further increase the dynamic range for NIR light.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.

Abstract: Threshold voltage (Vt) tuning layers may be sensitive to etching by reactants used to deposit overlying gate material, such as metal nitride. Methods for depositing Vt tuning layers are provided. In some embodiments Vt tuning layers may comprise a Vt tuning material in a neutral matrix. In some embodiments, processes for reducing or eliminating the etching of Vt tuning layers by halide reactants are described. In some embodiments a Vt tuning layer, such as a metal oxide layer, is treated by a nitridation process following deposition and prior to subsequent deposition of a metal nitride capping layer. In some embodiments an etch-protective layer, such as a NbO layer, is deposited over a Vt tuning layer prior to deposition of an overlying metal nitride layer.

Abstract: Various embodiments of the present disclosure are directed to a stacked complementary metal-oxide semiconductor (CMOS) image sensor. A first integrated circuit (IC) chip and a second IC chip are vertically stacked. A pixel sensor spans the first and second IC chips. The pixel sensor comprises a first transfer transistor and a photodetector that are at the first IC chip, and further comprises a source-follower transistor, a transistor capacitor, and a second transfer transistor that are at the second IC chip. The transistor capacitor and the second transfer transistor are electrically coupled in series from a source/drain region of the first transfer transistor to a gate electrode of the source-follower transistor.

Abstract: The present disclosure relates to a multi-dimensional image sensor integrated chip (IC) structure. The multi-dimensional image sensor IC structure includes a plurality of image sensing elements disposed within a plurality of pixel regions arranged in a pixel array of a first integrated chip (IC) tier. The plurality of pixel regions include a plurality of active pixel regions and one or more dummy pixel regions. A plurality of pixel support devices are disposed on a second substrate within a second IC tier that is bonded to the first IC tier. A plurality of logic devices are disposed within a third IC tier that is bonded to the second IC tier. A through substrate via (TSV) extends vertically through the second substrate laterally outside of the plurality of pixel support devices and directly below the pixel array.

Abstract: An image sensor includes a substrate including a first surface and a second surface opposite to the first surface; a plurality of pixel sensors disposed in the substrate, a sensor isolation feature disposed in the substrate defining an active region, and a dielectric layer between the sensor isolation feature and the substrate, wherein the sensor isolation feature comprises a conductive material.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a first integrated circuit (IC) die stacked with a second IC die. The first IC die includes a plurality of photodetectors disposed within a first substrate. The second IC die includes a plurality of pixel transistors and a semiconductor capacitor disposed on a second substrate. The semiconductor capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a doped capacitor region. The first capacitor electrode overlies the second substrate and comprises a protrusion disposed in the second substrate. The capacitor dielectric layer is disposed between the first capacitor electrode and the second substrate. The doped capacitor region is disposed within the second substrate and underlies the first capacitor electrode. The plurality of photodetectors, the plurality of pixel transistors, and the semiconductor capacitor define a pixel.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure.

Abstract: Some embodiments relate to a method that includes depositing a first layer of hard mask material over a layer of dielectric material; etching the first layer of the hard mask material, the etched first layer of hard mask material including an etched portion having a first lateral dimension; depositing a second layer of the hard mask material over the first layer of the hard mask material; etching at least a portion of the second layer of the hard mask material, while allowing a remaining portion of the hard mask material, to expose a portion of the layer of the dielectric material that has a second lateral dimension less than the first lateral dimension; and etching a trench into the layer of the dielectric material at the exposed portion of the layer of the dielectric material.

Abstract: An image sensor includes photosensitive areas in a first array within a semiconductor substrate. Microlens are disposed over the semiconductor substrate in a second array. Metal shields are disposed between a subset of the microlenses and corresponding photosensitive areas. The metal half-shields have dimensions and positions that provide half-shielding that enables half-shield phase detection autofocus. An antireflective coating is disposed over the metal half-shields. The metal half-shields and the antireflective coating may be in a composite grid that provides lateral separation between color filters. Alternatively, metal half-shields and the antireflective coating may be in below a layer that includes color filters. The antireflective coating includes a quarter-wave layer.

Abstract: A p-type doping region around an isolation structure provides additional electrical isolation between pixel sensors of a pixel array. As a result, current leakage from a floating node of one pixel sensor into another is reduced. Therefore, dark current is reduced, and performance of the pixel array is improved. Additionally, pixel noise caused by electrons trapped in the isolation structure may be reduced.

Abstract: A semiconductor image-sensing structure includes a reflective grid and a reflective shield disposed over a substrate. The reflective grid is disposed in a first region, and the reflective shield is disposed in a second region separated from the first region. A thickness of the reflective shield is greater than a thickness of the reflective grid.

Abstract: A semiconductor device includes a substrate having a front side and a back side opposite to each other. A plurality of photodetectors is disposed in the substrate within a pixel region. An isolation structure is disposed within the pixel region and between the photodetectors. The isolation structure includes a back side isolation structure extending from the back side of the substrate to a position in the substrate. A conductive plug structure is disposed in the substrate within a periphery region. A conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. A conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed on a first side of a substrate. A second via is disposed on the first side of the substrate and is laterally separated from the first via. An interconnect wire vertically contacts the second via. A through-substrate via (TSV) extends through the substrate to physically contact one or more of the second via and the interconnect wire. The first via has a first width and the second via has a second width. The second width is between approximately 2,000% and approximately 5,000% larger than the first width.