Abstract: In some embodiments, the present disclosure relates to an image sensor including a substrate having a first side and a second side opposite the first side; a photodetector region within the substrate; a gate structure on the first side of the substrate over the photodetector region; a deep trench isolation (DTI) structure surrounding the photodetector region and extending from the first side of the substrate to the second side; a doped floating node region within the substrate at the first side and disposed between the gate structure and the DTI structure; and a floating node on the first side of the substrate, contacting a top surface of the DTI structure and overlying the doped floating node region.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a bond pad structure extends to a columnar structure with a high via density. For example, an interconnect structure is on a frontside of a substrate and comprises a first bond wire, a second bond wire, and bond vias forming the columnar structure. The bond vias extend from the first bond wire to the second bond wire. The bond pad structure is inset into a backside of the substrate, opposite the frontside, and extends to the first bond wire. A projection of the first or second bond wire onto a plane parallel to a top surface of the substrate has a first area, and a projection of the bond vias onto the plane has a second area that is 10% or more of the first area, such that via density is high.

Abstract: In some embodiments, the present disclosure relates to an integrated device, including a substrate; an interconnect structure disposed over the substrate, the interconnect structure including an dielectric; a first bottom electrode structure disposed in the dielectric, the first bottom electrode structure having a first width as measured between outer sidewalls of the first bottom electrode structure and a first depth as measured from an upper surface of the dielectric; and a second bottom electrode structure disposed in the dielectric and spaced apart from the first bottom electrode structure, the second bottom electrode structure having a second width as measured between outer sidewalls of the second bottom electrode structure and a second depth as measured from the upper surface of the dielectric; where the first width is greater than the second width and the first depth is greater than the second depth.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: A semiconductor image sensing structure includes a substrate having a first region and a second region, a metal grid in the first region, and a hybrid metal shield in the second region. The hybrid metal shield includes a first metallization layer, a second metallization layer disposed over the first metallization layer, a third metallization layer disposed over the second metallization layer, and a fourth metallization layer disposed over the third metallization layer. An included angle of the second metallization layer is between approximately 40° and approximately 60°.

Abstract: An image sensor includes a substrate including a first surface and a second surface opposite to the first surface; a plurality of pixel sensors disposed in the substrate, a sensor isolation feature disposed in the substrate defining an active region, and a dielectric layer between the sensor isolation feature and the substrate, wherein the sensor isolation feature comprises a conductive material.

Abstract: A metal grid within a trench isolation structure on the back side of an image sensor is coupled to a contact pad so that a voltage on the metal grid is continuously variable with a voltage on the contact pad. One or more conductive structures directly couple the metal grid to a contact pad. The conductive structures may bypass a front side of the image sensor. A bias voltage on the metal grid may be varied through the contact pad whereby a trade-off between reducing cross-talk and increasing quantum efficiency may be adjusted dynamically in accordance with the application of the image sensor, its environment of use, or its mode of operation.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.

Abstract: An embodiment high-density capacitor includes a bottom electrode having a plurality of non-concentric cylindrical portions, a top electrode including a plurality of vertical portions and a surrounding portion, and a dielectric layer separating the top electrode from the bottom electrode. Each of the plurality of non-concentric cylindrical portions includes an inner shell and an outer shell and each of the plurality of vertical portions is vertically surrounded by the inner shell of a respective cylindrical portion of the bottom electrode. The surrounding portion of the top electrode respectively vertically surrounds each of the plurality of non-concentric cylindrical portions of the bottom electrode such that adjacent non-concentric cylindrical portions of the bottom electrode are separated from one another by the surrounding portion of the top electrode. At least some of the plurality of non-concentric cylindrical portions of the bottom electrode include a spatial distribution having a hexagonal symmetry.

Abstract: An optical device and a method of fabricating the same are disclosed. The optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite to the first surface, first and second pixel structures, an inter-pixel isolation structure disposed in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. The second die layer includes a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.

Abstract: A process used to form a first deep trench isolation (DTI) structure in a pixel region of a semiconductor substrate is also used to form a second DTI structure in a guard ring area that isolates the pixel region from a peripheral region. The guard ring area may have a PNP guard ring structure. The second DTI structure may include trenches in each of an inner ring, a middle, and an outer ring of the PNP guard ring structure. The first and second DTI structures may have conductive cores. The conductive cores of the inner and outer ring may be biased to a first voltage while the conductive cores of the middle ring may be biased to an opposite polarity second voltage. When the second DTI structure have conductive cores with these biases, the second DTI structure may be used as the guard ring without the PNP structure.

Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.

Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.

Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.

Abstract: A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.

Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a bond pad structure extends to a columnar structure with a high via density. For example, an interconnect structure is on a frontside of a substrate and comprises a first bond wire, a second bond wire, and bond vias forming the columnar structure. The bond vias extend from the first bond wire to the second bond wire. The bond pad structure is inset into a backside of the substrate, opposite the frontside, and extends to the first bond wire. A projection of the first or second bond wire onto a plane parallel to a top surface of the substrate has a first area, and a projection of the bond vias onto the plane has a second area that is 10% or more of the first area, such that via density is high.