Abstract: The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance.

Abstract: The present disclosure relates to semiconductor device with a multi-gate structure. The semiconductor device includes a substrate and a doped region disposed within the substrate. A gate electrode is disposed over the doped region, and a source region and a drain region are disposed within the doped region. A shallow trench isolation (STI) structure is disposed within the substrate and laterally surrounds the source region and the drain region. A first doped liner is disposed along the STI structure, where the first doped liner separates the STI structure from the source region and the drain region. A second doped liner is disposed along the STI structure, where the second doped liner is separated from the first doped liner by the STI structure above a bottom surface of the STI structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.

Abstract: A semiconductor device structure includes a first chip, second chip, a first metal structure, a second metal structure, a first via structure and a second via structure. The first chip includes n inter metal dielectric (IMD) layer, which includes different materials adjacent to generate a number of staggered portions having a zigzag configuration. The second chip bonded to the first chip generates a bonding interface. The first metal structure is disposed in the first chip and between the staggered portions and the bonding interface. The first via structure in the first chip stops at the first metal structure. The first via structure includes a first via metal and a first via dielectric layer. A surface roughness of the staggered portions is substantially greater than a surface roughness of the first via dielectric layer. The second via structure extends from the first via structure to the second metal structure.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

Abstract: The present disclosure relates to an image sensor integrated chip (IC). The image sensor IC includes one or more interconnects arranged within an inter-level dielectric (ILD) structure on a first side of a substrate. An image sensing element is arranged within the substrate. Sidewalls of the substrate form one or more trenches extending from a second side of the substrate to within the substrate on opposing sides of the image sensing element. A dielectric structure is arranged on the sidewalls of the substrate that form the one or more trenches. A conductive core is arranged within the one or more trenches and is laterally separated from the substrate by the dielectric structure. The conductive core is electrically coupled to the one or more interconnects.

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: The present disclosure describes an image sensor and a method for forming the image sensor. The image sensor includes an image sensing element disposed on a substrate, an extension pad disposed adjacent to the image sensing element, and a polysilicon pillar disposed on the extension pad. The image sensor further includes an insulating layer disposed over the image sensing element, the extension pad, and the polysilicon pillar.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.

Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

Abstract: An atomic layer deposition (ALD) method can include pulsing a first reactant vapor into a reactor assembly. The first reactant vapor is supplied to a first reactant gas line. An inactive gas is supplied to a first inactive gas line at a first flow rate. The first reactant vapor and the inactive gas are fed to the reactor assembly by way of a first feed line. The reactor assembly is purged by supplying the inactive gas to the first inactive gas line at a second flow rate higher than the first flow rate. A first portion of the inactive gas can be fed back along a diffusion barrier portion of the first reactant gas line to provide an inert gas valve (IGV) upstream of the first inactive gas line. A second portion of the inactive gas can be fed to the reactor assembly by way of the first feed line.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects within a first dielectric structure on a first substrate, and a second plurality of interconnects within a second dielectric structure on a second substrate. A bonding structure is arranged between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends between the first plurality of interconnects and the second plurality of interconnects and through the second substrate. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region surrounded by the bonding structure. The second region contacts a bottom of the first region and has tapered sidewalls.

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

Abstract: In some embodiments, the present disclosure relates to a method for forming an image sensor and associated device structure. A backside deep trench isolation (BDTI) structure is formed in a substrate separating a plurality of pixel regions. The BDTI structure encloses a plurality of photodiodes and comprising a first BDTI component arranged at a crossroad of the plurality of pixel regions and a second BDTI component arranged at remaining peripheries of the plurality of pixel regions. The first BDTI component has a first depth from a backside of the substrate smaller than a second depth of the second BDTI component.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.

Abstract: Image sensors and processes of forming the same are provided. An image sensor according to the present disclosure includes a first photodiode disposed between a second photodiode and a third photodiode along a direction, a first deep trench isolation (DTI) feature disposed between the first photodiode and the second photodiode, and a second DTI feature disposed between the first photodiode and the third photodiode. A depth of the first DTI feature is greater than a depth of the second DTI feature. A quantum efficiency of the second photodiode is smaller than a quantum efficiency of the first photodiode.