Patents by Inventor Jen-Chou Tseng
Jen-Chou Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352338Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.Type: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Inventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
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Patent number: 11742236Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.Type: GrantFiled: November 30, 2020Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
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Publication number: 20220359648Abstract: A circuit device includes core circuitry. The circuit device further includes a first plurality of guard rings having a first dopant type, wherein the first plurality of guard rings is around a periphery of the core circuitry. The circuit device further includes a second plurality of guard rings having a second dopant type, wherein the second dopant type is opposite to the first dopant type, and at least one guard ring of the second plurality of guard rings is around a periphery of at least one guard ring of the first plurality of guard rings.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Wan-Yen LIN, Wun-Jie LIN, Yu-Ti SU, Bo-Ting CHEN, Jen-Chou TSENG, Kuo-Ji CHEN, Sun-Jay CHANG, Min-Chang LIANG
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Patent number: 11450735Abstract: A method includes implanting a first guard ring around a periphery of core circuitry. The implanting of the first guard ring includes implanting a first component a first distance from the core circuitry on a first side of the core circuitry, and implanting a second component a second distance from the core circuitry on a second side of the core circuitry, wherein the second distance is greater than the first distance. The method further includes implanting a second guard ring around the periphery of the core circuitry. The implanting of the second guard ring includes implanting a third component a third distance from the core circuitry on the first side of the core circuitry, and implanting a fourth component a fourth distance from the core circuitry on the second side of the core circuitry, wherein the third distance is greater than the fourth distance.Type: GrantFiled: November 19, 2020Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wan-Yen Lin, Wun-Jie Lin, Yu-Ti Su, Bo-Ting Chen, Jen-Chou Tseng, Kuo-Ji Chen, Sun-Jay Chang, Min-Chang Liang
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Patent number: 11264374Abstract: A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.Type: GrantFiled: August 18, 2020Date of Patent: March 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song
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Patent number: 10991442Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.Type: GrantFiled: September 8, 2020Date of Patent: April 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-Yu Chou, Yu-Ti Su
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Patent number: 10964651Abstract: An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies.Type: GrantFiled: December 21, 2018Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Chou Tseng, Tzu-Heng Chang
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Publication number: 20210091176Abstract: A method includes implanting a first guard ring around a periphery of core circuitry. The implanting of the first guard ring includes implanting a first component a first distance from the core circuitry on a first side of the core circuitry, and implanting a second component a second distance from the core circuitry on a second side of the core circuitry, wherein the second distance is greater than the first distance. The method further includes implanting a second guard ring around the periphery of the core circuitry. The implanting of the second guard ring includes implanting a third component a third distance from the core circuitry on the first side of the core circuitry, and implanting a fourth component a fourth distance from the core circuitry on the second side of the core circuitry, wherein the third distance is greater than the fourth distance.Type: ApplicationFiled: November 19, 2020Publication date: March 25, 2021Inventors: Wan-Yen LIN, Wun-Jie LIN, Yu-Ti SU, Bo-Ting CHEN, Jen-Chou TSENG, Kuo-Ji CHEN, Sun-Jay CHANG, Min-Chang LIANG
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Patent number: 10957687Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.Type: GrantFiled: March 13, 2020Date of Patent: March 23, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
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Publication number: 20210082743Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
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Publication number: 20200402599Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.Type: ApplicationFiled: September 8, 2020Publication date: December 24, 2020Inventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-Yu Chou, Yu-Ti Su
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Patent number: 10868112Abstract: A circuit device includes core circuitry. The circuit device further includes a guard ring surrounding the core circuitry. The guard ring includes a first plurality of fin structures arranged in a first direction parallel to a first side of the core circuitry, wherein adjacent fin structures of the first plurality of fin structures are separated by a first distance. The guard ring further includes a second plurality of fin structures arranged in a second direction parallel to a second side of the core circuitry, wherein adjacent fin structures of the second plurality of fin structures are separated by a second distance, and the second distance is smaller than the first distance.Type: GrantFiled: November 9, 2018Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wan-Yen Lin, Wun-Jie Lin, Yu-Ti Su, Bo-Ting Chen, Jen-Chou Tseng, Kuo-Ji Chen, Sun-Jay Chang, Min-Chang Liang
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Publication number: 20200381419Abstract: A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.Type: ApplicationFiled: August 18, 2020Publication date: December 3, 2020Inventors: Tzu-Heng CHANG, Jen-Chou TSENG, Ming-Hsiang SONG
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Patent number: 10854501Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.Type: GrantFiled: June 28, 2018Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
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Patent number: 10803967Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.Type: GrantFiled: March 26, 2020Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-Yu Chou, Yu-Ti Su
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Patent number: 10756082Abstract: A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.Type: GrantFiled: June 17, 2019Date of Patent: August 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song
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Publication number: 20200227126Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-Yu Chou, Yu-Ti Su
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Publication number: 20200219868Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.Type: ApplicationFiled: March 13, 2020Publication date: July 9, 2020Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
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Patent number: 10643726Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.Type: GrantFiled: April 24, 2019Date of Patent: May 5, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-yu Chou, Yu-Ti Su
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Patent number: 10629588Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.Type: GrantFiled: November 28, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang