Abstract: According to an embodiment, a semiconductor device is provided. The device includes a second region having a greater curvature than a first region. The device includes an epitaxy layer of a first conductivity type, a well of a second conductivity type in the epitaxy layer, a drain in the epitaxy layer, a source in the well, and a bulk in the well and in contact with the source, the bulk having a greater area in the second region than in the first region.

Abstract: A method and structure of improving the robustness of an electrostatic discharge (ESD) protection device is disclosed. One aspect of the instant disclosure provides a semiconductor structure that comprises: a first well structure; a second well structure arranged adjacent to the isolation structure in the substrate, a diffusion region respectively disposed in the first and the second well structures; an isolation structure arranged between the well structures and laterally separating the diffusion regions; and a partition structure arranged in the isolation structure. The partition structure affects a steeper slope on a lateral surface of the isolation structure bordering at least one of the diffusion regions, thereby modifying a ballasting characteristic of the isolation structure.

Abstract: A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material.

Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

Abstract: The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, and an ESD detection circuit coupled to the common trigger line and to a first power line common to the other dies, wherein when the ESD detection circuit of one of the plural dies detects an ESD event, the ESD detection circuit is configured to generate a control signal to the common trigger line to control a power clamp in each of the plural dies to clamp an ESD event to the common first power line or a second power line.

Abstract: An electrostatic discharge (ESD) testing structure includes a measurement device in a first die. The ESD testing structure further includes a fuse in a second die. The ESD testing structure further includes a plurality of bonds electrically connecting the first die to the second die, wherein a first bond of the plurality of bonds electrically connects the fuse to the measurement device.

Abstract: An ESD protection circuit for an RF circuit includes first and second power supply voltage terminals for first and second power supply voltages and a power clamp coupled between the terminals. An RF input pad is configured to receive an input signal having an RF operating frequency. A resonance circuit is coupled to the RF input pad. A first ESD current path from the RF input pad to the first power supply voltage terminal includes the resonance circuit and a first ESD block configured to direct an ESD pulse of a first polarity toward the first terminal. A second ESD current path from the RF input pad to the second power supply voltage terminal includes the resonance circuit and a second ESD block configured to direct an ESD pulse of a second polarity toward the second terminal.

Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

Abstract: A chip includes a first die, a second die, a first and a second through-silicon vias, a first protection circuit, and a second protection circuit. The first die has a first operational voltage node and a first reference voltage node. The second die has a second operational voltage node and a second reference voltage node. The first and the second through-silicon vias are configured to couple the first die and the second die. The first protection circuit is coupled between the first operational voltage node and the first through-silicon via. The second protection circuit is coupled between the first reference voltage node and the second through-silicon via. The first through-silicon via is further coupled to the second reference voltage node or the second operational voltage node. The second through-silicon via is further coupled to the first reference voltage node or the first operational voltage node.

Abstract: A voltage detector includes a first node configured to have a first supply voltage, a second node configured to have a second supply voltage, and an output node. The voltage detector is configured to drive the output node to the first supply voltage in response to a difference between the first supply voltage and the second supply voltage exceeding a predetermined threshold voltage value.

Abstract: According to an embodiment, a semiconductor device is provided. The device includes a second region having a greater curvature than a first region. The device includes an epitaxy layer of a first conductivity type, a well of a second conductivity type in the epitaxy layer, a drain in the epitaxy layer, a source in the well, and a bulk in the well and in contact with the source, the bulk having a greater area in the second region than in the first region.

Abstract: According to an embodiment, a semiconductor device is provided. The device includes: The second region has a greater curvature than the first region. The device includes: an N-type epitaxy layer; a P-well in the N-type epitaxy layer; a drain in the N-type epitaxy layer; a source in the P-well; and a bulk in the P-well and in contact with the source, wherein the bulk has a greater area in the second region than in the first region.

Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.

Abstract: A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material.

Abstract: One or more electrostatic discharge (ESD) control circuit are disclosed herein. In an embodiment, an ESD control circuit has first and second trigger transistors, first and second ESD transistors, and first and second feedback transistors. The ESD transistors provide ESD current paths for ESD current generated during an ESD event. The first and second trigger transistors are on during normal operation to maintain the ESD transistors in an off state. During an ESD event, the first and second transistors are turned off to enable the first and second ESD transistors to provide ESD current paths. The first and second feedback transistors turn on during an ESD event to reinforce the on state of the ESD transistors and to reinforce the off state of the trigger transistors. In this way, the ESD control circuit stably provides multiple ESD current paths to discharge ESD current.

Abstract: An ESD protection system for an internal circuit is disclosed. The ESD protection system comprises an ESD clamping device connected between a pad and a ground of a first domain); a pre-driver having an output coupled to a gate of the ESD clamping device); an ESD control circuit connected between the pre-driver and the internal circuit; and a transient detection unit coupled to the ESD control circuit, configured to detect an ESD transient from the pad of the first domain. The transient detection unit outputs an first signal to the control circuit upon detection of an ESD transient. In response, the control circuit causes the pre-driver to output a high-impedance state at the gate of the ESD clamping device, thereby floating the gate thereof.

Abstract: A circuit includes a first node having a first supply voltage, a second node having a second supply voltage, and a voltage detector coupled between the first node and the second node, the voltage detector including a first output node. A clamp circuit is coupled between the first node and the second node. The voltage detector is configured to drive the first output node to the first supply voltage in response to a difference between the first supply voltage and the second supply voltage exceeding a predetermined threshold voltage value. The clamp circuit is configured to establish a conduction path between the first node and the second node in response to the first or second output node being driven to the first supply voltage.

Abstract: A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material.

Abstract: According to an embodiment, a semiconductor device is provided. The device includes: The second region has a greater curvature than the first region. The device includes: an N-type epitaxy layer; a P-well in the N-type epitaxy layer; a drain in the N-type epitaxy layer; a source in the P-well; and a bulk in the P-well and in contact with the source, wherein the bulk has a greater area in the second region than in the first region.