Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

Abstract: A bonding apparatus with a bonding head having vacuum channels and switchable channels, and the method of forming the same are provided. The bonding apparatus may include a vacuum pump, a blower, a controller communicatively coupled to the vacuum pump and the blower, and a bonding head. The bonding head may include a main body, a first vacuum channel in the main body, wherein the first vacuum channel is connected to the vacuum pump, and a first switchable channel in the main body, wherein the first switchable channel is connected to the vacuum pump and the blower.

Abstract: A die bonding tool includes a bond head having a moveable component. The moveable component may be moveable between an extended position in which a lower surface of the moveable component protrudes below a lower surface of the bond head and a retracted position in which the lower surface of the moveable component does not protrude below the lower surface of the bond head. The moveable component may be used to control a shape of a semiconductor die secured to the lower surface of the bond head during a process of bonding the semiconductor die to a substrate. Accordingly, void areas and other bonding defects may be avoided and the bond formed between the semiconductor die and the target substrate may be improved.

Abstract: A bonded assembly may be formed by performing a chip plasma clean process on a semiconductor chip; generating at least one chip infrared image of a cleaned side of the semiconductor chip; measuring an average emissivity of at least one metallic region in the at least one chip infrared image; performing a subsequent processing step selected from a bonding step and an alternative processing step based on the measured average emissivity. The bonding step is performed if the measured average emissivity is less than a predetermined emissivity threshold value. The alternative processing step is performed if the measured average emissivity is greater than the predetermined emissivity threshold value. The alternative processing step may be selected from an additional clean step and an additional inspection step.

Abstract: A bonded assembly may be formed by: providing a substrate and a semiconductor chip in a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa; disposing the semiconductor chip on the substrate; performing a plasma treatment process on a copper-containing surface of a chip bonding pad on the semiconductor chip in the low-oxygen ambient by directing a plasma jet to the chip bonding pad; and attaching a bonding wire to the semiconductor chip and to the substrate such that a first end of the bonding wire is attached to the copper-containing surface and a second end of the bonding wire is attached to a substrate bonding pad on the substrate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

Abstract: In an embodiment, a system includes: a circular frame comprising a first side and a second side opposite the first side, wherein the circular frame comprises an aperture formed therethrough; an insert disposed within the aperture; a first wafer disposed over the insert; a second wafer disposed over the first wafer, wherein both the first wafer and the second wafer are configured for eutectic bonding when heated; two clamps disposed on the first side along the circular frame, wherein the two clamps are configured to contact the second wafer at respective clamp locations; and a plurality of pieces configured to secure the insert within the aperture, the plurality of pieces comprising both fixed and flexible pieces, the plurality of pieces comprising two fixed pieces disposed respectively adjacent to the clamp locations along the second side of the circular frame.

Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.

Abstract: A microelectromechanical systems (MEMS) package with roughness for high quality anti-stiction is provided. A device substrate is arranged over a support device. The device substrate comprises a movable element with a lower surface that is rough and that is arranged within a cavity. A dielectric layer is arranged between the support device and the device substrate. The dielectric layer laterally encloses the cavity. An anti-stiction layer lines the lower surface of the movable element. A method for manufacturing the MEMS package is also provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first wafer comprising a first face and a second face opposite the first face and having a plurality of predetermined die areas. A plurality of recesses are disposed in the first face of the first wafer. A first recess of the plurality of recesses extends in a direction substantially parallel to a first edge of at least one of the plurality of predetermined die areas and laterally surrounds the at least one of the plurality of predetermined die areas. A second wafer is bonded to the second face of the first wafer.

Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.

Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.

Abstract: The present disclosure relates to a method for manufacturing a microelectromechanical systems (MEMS) package. The method comprises providing a CMOS IC including CMOS devices arranged within a CMOS substrate. The method further comprises forming and patterning a metal layer over the CMOS substrate to form an anti-stiction layer and a fixed electrode plate and forming a rough top surface for the anti-stiction layer. The method further comprises providing a MEMS IC comprising a moveable mass arranged within a recess of a MEMS substrate and bonding the CMOS IC to the MEMS IC to enclose a cavity between the moveable mass and the fixed electrode plate and the anti-stiction layer.

Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first wafer comprising a first face and a second face opposite the first face and having a plurality of predetermined die areas. A plurality of recesses are disposed in the first face of the first wafer. A first recess of the plurality of recesses extends in a direction substantially parallel to a first edge of at least one of the plurality of predetermined die areas and laterally surrounds the at least one of the plurality of predetermined die areas. A second wafer is bonded to the second face of the first wafer.

Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.

Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.

Abstract: A blood glucose test strip includes a test strip, a blood test area formed on a first end of the test strip, an electrode formed on a second end of the test strip, a data barcode formed on the test strip, and a clock code formed on the test strip. The data barcode may include a plurality of first bars with spaces separating the first bars, each first bar having a width. The clock code may comprise a fixed pattern of second bars with spaces separating the second bars, a width of each second bar set according to the width of at least one of the first bars. The clock code can be used to calibrate the data barcode to compensate for insertion speed and/or moisture content.