Abstract: A method of forming dense hole patterns of semiconductor devices includes: forming a plurality of first pillars on at least one lower hard mask layer disposed on a substrate; forming a spacer layer on the lower hard mask layer to form a plurality of second pillars respectively covering the first pillars, wherein a plurality of first holes are formed among the second pillars; etching the spacer layer to expose first portions of the lower hard mask layer via the first holes and expose top surfaces of the first pillars; removing the first pillars to form a plurality of second holes in the spacer layer to expose second portions of the lower hard mask layer; etching the first portions and the second portions of the lower hard mask layer at least until portions of the substrate are exposed; and removing remaining portions of the spacer layer.

Abstract: A method of forming dense hole patterns of semiconductor devices includes: forming a plurality of first pillars on at least one lower hard mask layer disposed on a substrate; forming a spacer layer on the lower hard mask layer to form a plurality of second pillars respectively covering the first pillars, wherein a plurality of first holes are formed among the second pillars; etching the spacer layer to expose first portions of the lower hard mask layer via the first holes and expose top surfaces of the first pillars; removing the first pillars to form a plurality of second holes in the spacer layer to expose second portions of the lower hard mask layer; etching the first portions and the second portions of the lower hard mask layer at least until portions of the substrate are exposed; and removing remaining portions of the spacer layer.

Abstract: A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.

Abstract: A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench.

Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.

Abstract: A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.

Abstract: A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3.

Abstract: An exemplary memory device includes a substrate and two word lines extending on the substrate. The substrate includes an active area. The two word lines are formed on the active area. Each word line includes a recessed portion corresponding to the active area. The recessed portion is defined by a planar top surface.

Abstract: A memory device includes a substrate, first and second trench isolations, a plurality of line-type isolations, a first word line, and a second word line. The substrate comprises an active area having source and drain regions. The first and second trench isolations extend parallel to each other. The line-type isolations define the active area together with the first and second trench isolations. The first word line extends across the active area and is formed in the substrate adjacent to the first trench isolation defining a first segment of the active area with the first trench isolation. The second word line extends across the active area and is formed in the substrate adjacent to the second trench isolation defining a second segment of the active area with the second trench isolation. The size of the first segment is substantially equal to the size of the second segment.

Abstract: A memory device includes a substrate, first and second trench isolations, a plurality of line-type isolations, a first word line, and a second word line. The substrate comprises an active area that comprises source and drain regions. The first and second trench isolations extend parallel to each other. The plurality of line-type isolations define the active area together with the first and second trench isolations. The first word line extends across the active area. The first word line is formed in the substrate and adjacent to the first trench isolation. The first word line defines a first segment of the active area with the first trench isolation. The second word line extends across the active area. The second word line is formed in the substrate and adjacent to the second trench isolation. The second word line defines a second segment of the active area with the second trench isolation. The size of the first segment is substantially equal to the size of the second segment.

Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.

Abstract: A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench.

Abstract: A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.

Abstract: A method for forming a ring pattern is disclosed. The ring pattern has a first wall and a second wall. The method includes the following steps: (a) providing a substrate; (b) forming a dielectric layer on the substrate; (c) forming a first patterned photoresist layer on the dielectric layer, the first patterned photoresist layer defining the first wall; (d) etching the dielectric layer to a predetermined depth by using the first patterned photoresist as a mask, and then removing the first patterned photoresist layer; (e) forming a second patterned photoresist layer on the dielectric layer, the second patterned photoresist layer defining the second wall; (f) etching the dielectric layer by using the second patterned photoresist layer as a mask so as to form the ring pattern having the first wall and the second wall.

Abstract: A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.

Abstract: A flash memory including a substrate having a recess, a buried bit line, a word line, a single side insulating layer, a floating gate, a tunneling dielectric layer, a control gate, and an inter-gate dielectric layer is provided. The buried bit line extends below the recess of the substrate along a first direction. The word line is on the substrate, and extends above the recess along a second direction. The single side insulating layer is on a first sidewall of the recess. The floating gate is on a second sidewall of the recess to be opposite to the single side insulating layer. The tunneling dielectric layer is sandwiched by the floating gate and the substrate to contact the buried bit line. The control gate fills the recess and contacts the word line. The inter-gate dielectric layer is sandwiched by the control gate and the floating gate.

Abstract: A dynamic random access memory (DRAM) structure has a stacked capacitor disposed above an upper source/drain region of a vertical transistor having a surrounding gate. The gates of each row of a memory array are electrically connected with a buried word line. Each of bit lines is disposed between two adjacent columns of transistors and electrically connected with lower source/drain regions through bit line contacts. The DRAM structure may have a unit cell size of 4F2.

Abstract: A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench.

Abstract: A method for fabricating a conductive plug includes the steps of providing a substrate having at least a gate structure thereon, a first dielectric layer covering a surface of the substrate, a second dielectric layer disposed on the first dielectric layer, and at least a metal line formed within the second dielectric layer; forming a hard mask plug on the second dielectric layer; forming a third dielectric layer covering the second dielectric layer and the hard mask plug; removing a portion of the third dielectric layer to expose the hard mask plug; removing the hard mask plug to form a plug hole; and forming the conductive plug within the plug hole to electrically connect with the gate structure.

Abstract: An interconnect process is provided. A substrate is provided. A plurality of gate structures is disposed on the substrate, and doped regions are disposed in the substrate and respectively located between two adjacent gate structure. A liner is conformally formed above the substrate. A dielectric layer is formed above the substrate. A contact opening is formed in the dielectric layer between two neighboring gate structures to expose the liner on the doped region and on a portion of the top surface and a portion of the sidewall of each of the gate structures. A polymer material is deposited on the liner on the portion of the top surface of each of the gate structures and on the doped region. The liner on the doped regions is removed. A conductive layer is filled in the contact opening, which is free of electrical connection to the gate structures.