SEMICONDUCTOR MEMORY ARRAY STRUCTURE
A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3.
1. Field of the Invention
The present invention relates to a semiconductor memory array structure, and more particularly to a memory array having independent depth-controlled shallow trench isolation, and methods of manufacturing the same.
2. Description of the Prior Art
As well known in the art, a shallow trench isolation structure comprises a dielectric material that laterally surrounds active areas (AA) of a semiconductor substrate comprising a semiconductor material, which is typically silicon. Typically, the shallow trench isolation structure is formed by first patterning a shallow trench that laterally surrounds the active area, followed by deposition of a dielectric material into the shallow trench and a subsequent planarization of the deposited dielectric material. The dielectric material is typically removed from above the active areas during the planarization step, and the remaining portions of the dielectric material within the shallow trench constitute the shallow trench isolation structure.
Conventionally, the aforesaid shallow trench that laterally surrounds the active area is formed by using a single lithographic process and a single dry etching process. That is, only one photomask (i.e., AA photomask) that defines the AA pattern thereon is used during the lithographic process, and the shallow trench has substantially the same depth. However, due to the line shortening effect and/or other optical interference effects, the AA pattern transferred to the photoresist or the underlying substrate has an oval-like shape that has a smaller surface area than the original pattern that defined on the AA photomask. This adversely affects the process window and the electric performance of the semiconductor device fabricated in the AA regions.
SUMMARY OF THE INVENTIONIn one aspect, the present invention provides a memory array including a plurality of rhomboid-shaped active area (AA) regions in a substrate, each of the rhomboid-shaped AA regions having a pair of longer sides and a pair of shorter sides; a first shallow trench isolation (STI) structure extending along a first direction on the longer sides of the rhomboid-shaped AA region, wherein the first STI structure has a depth d1; and a second STI structure extending along the second direction on the shorter sides of the rhomboid-shaped AA region, wherein the second STI structure has two depths: d2 and d3, wherein d1 and d2 are shallower than d3.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings are exaggerated or reduced in size, for the sake of clarity and convenience. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
DETAILED DESCRIPTIONIn the following description, numerous specific details are given to provide a thorough understanding of the invention. It will, however, be apparent to one skilled in the art that the invention may be practiced without these specific details. Furthermore, some well-known system configurations and process steps are not disclosed in detail, as these should be well-known to those skilled in the art.
Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and some dimensions are exaggerated in the figures for clarity of presentation. Also, where multiple embodiments are disclosed and described as having some features in common, like or similar features will usually be described with like reference numerals for ease of illustration and description thereof.
Please refer to
Subsequently, as shown in
Please refer to
As shown in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A memory array, comprising:
- a plurality of rhomboid-shaped active area (AA) regions in a substrate, each of the rhomboid-shaped AA regions having a pair of longer sides and a pair of shorter sides;
- a first shallow trench isolation (STI) structure extending along a first direction on the longer sides of the rhomboid-shaped AA region, wherein the first STI structure has a depth d1; and
- a second STI structure extending along a second direction on the shorter sides of the rhomboid-shaped AA region, wherein the second STI structure has two depths: d2 and d3, the depth d3 is the depth of overlapping regions where the first STI structure intersects the second STI structure, the depths d1, d2 and d3 are different, and the depths d1 and d2 are shallower than d3.
2. (canceled)
3. The memory array according to claim 1 wherein the second STI structure has the depth d2 in a sub-region located between the overlapping regions.
4. The memory array according to claim 1 wherein the depth d1 and the depth d2 range between 2300˜2600 angstroms.
5. The memory array according to claim 1 wherein the depth d3 ranges between 2600-2800 angstroms.
6. The memory array according to claim 1 wherein the substrate is a silicon substrate.
7. The memory array according to claim 1 wherein the first direction is not perpendicular to the second direction.
Type: Application
Filed: Sep 13, 2012
Publication Date: Mar 13, 2014
Inventors: Shian-Jyh Lin (New Taipei City), Jeng-Ping Lin (Taoyuan County), Chin-Piao Chang (New Taipei City), Jen-Jui Huang (Taoyuan County)
Application Number: 13/615,526
International Classification: H01L 27/00 (20060101);