Abstract: A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.

Abstract: A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.

Abstract: A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.

Abstract: A plasma damage protection circuit includes a word line driver circuit with plasma damage protection features. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the word line drivers to the semiconductor substrate. Another plasma-based protection circuit includes a device coupled to multiple word line drivers. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the device to the semiconductor substrate. Thus, these plasma-based protection circuits save space while protecting the integrated circuit from plasma process-based damage.

Abstract: A method of fabricating an array of trapped charge memory cells is described that eliminates bird's beak issues. Implants at a tilt angle form pockets in a substrate that reduce problems resulting from a short channel effect.

Abstract: A phase-change multi-level memory cell is described, including a semiconductor substrate, a gate structure, two S/D regions, and two phase-change storing units electrically connected to the two S/D regions respectively. One phase-change storing unit can be programmed to one of many phases having different electrical resistances, and combination variations of the phases of the two phase-change storing units generate different read currents corresponding to 2n n-bit data values (n>2). To program the cell, the phase of each phase-change storing unit is changed to one of the many phases mentioned above, so that the phase combination of the two phase-change storing units corresponds to a predetermined data value. In addition, when reading the memory cell, the read current is measured to obtain the data value stored.

Abstract: A plasma damage protection circuit includes a word line driver circuit with plasma damage protection features. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the word line drivers to the semiconductor substrate. Another plasma-based protection circuit includes a device coupled to multiple word line drivers. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the device to the semiconductor substrate. Thus, these plasma-based protection circuits save space while protecting the integrated circuit from plasma process-based damage.

Abstract: A layout of flash memory having symmetric select transistors includes a memory cell array and a polysilicon gate. The polysilicon gate forms a plurality of select transistors in coordination with a plurality of pairs of sources/drains, so as to connect to the memory cell array. The polysilicon is perpendicularly extended toward a direction of the memory cell array, thereby overcoming a drawback as select transistors being unsymmetrical in a prior flash memory structure.

Abstract: A layout of flash memory having symmetric select transistors includes a memory cell array and a polysilicon gate. The polysilicon gate forms a plurality of select transistors in coordination with a plurality of pairs of sources/drains, so as to connect to the memory cell array. The polysilicon is perpendicularly extended toward a direction of the memory cell array, thereby overcoming a drawback as select transistors being unsymmetrical in a prior flash memory structure.

Abstract: A semiconductor memory device is provided, including one or more bit lines, one or more word lines, and a dummy word line, which is coupled to a positive bias. A memory cell and dummy cell are coupled to a bit line and may be coupled to a word line and dummy word line respectively. Coupling the dummy word line to a positive bias at least during an erase operation prevents the dummy cells from being over-erased, which occurs when the dummy word line is coupled to ground.

Abstract: A semiconductor device that includes a semiconductor substrate including a memory cell region and a dummy cell region, a plurality of substantially parallel bit lines in the semiconductor substrate, a plurality of memory cell gate dielectrics provided over the bit lines in the memory cell region, the memory cell gate dielectrics comprising an oxide-nitrideoxide (ONO) layer, a plurality of dummy cell gate dielectrics provided over the plurality of bit lines in the dummy cell region, wherein the dummy cell gate dielectrics is non-trapping for electric charges, and a plurality of substantially parallel word lines over the memory cell gate dielectrics and the dummy cell gate dielectrics.

Abstract: Programming a flash memory cell comprises receiving a first Vt corresponding to a first bit stored in the flash memory cell and receiving a second Vt corresponding to a second bit stored in the flash memory cell. In additon, programming the flash memory cell comprises programming one of the first bit and the second bit of the flash memory cell with a first programming voltage if the first Vt and the second Vt both correspond to a low Vt state prior to programming the flash memory cell. Furthermore, the first programming voltage is &Dgr;V lower than a second programming voltage that is used to program one of the first bit and the second bit of the flash memory cell if either of the first Vt and the second Vt correspond to a high Vt state prior to programming the flash memory cell.

Abstract: Programming a flash memory cell comprises receiving a first Vt corresponding to a first bit stored in the flash memory cell and receiving a second Vt corresponding to a second bit stored in the flash memory cell. In additon, programming the flash memory cell comprises programming one of the first bit and the second bit of the flash memory cell with a first programming voltage if the first Vt and the second Vt both correspond to a low Vt state prior to programming the flash memory cell. Furthermore, the first programming voltage is &Dgr;V lower than a second programming voltage that is used to program one of the first bit and the second bit of the flash memory cell if either of the first Vt and the second Vt correspond to a high Vt state prior to programming the flash memory cell.

Abstract: A semiconductor memory device is provided, including one or more bit lines, one or more word lines, and a dummy word line, which is coupled to a positive bias. A memory cell and dummy cell are coupled to a bit line and may be coupled to a word line and dummy word line respectively. Coupling the dummy word line to a positive bias at least during an erase operation prevents the dummy cells from being over-erased, which occurs when the dummy word line is coupled to ground.

Abstract: A method for operating a memory cell of a multi-level NROM is described. The memory cell of the multi-level NROM comprises a nitride layer, wherein the nitride layer comprises a plurality of charge-trapping regions to store locally a plurality of charges as the first bit memory and the second bit of memory. The stored charges of the second bit of memory forms an electrical barrier, which in turns affects the size of the threshold electric current of the first bit. The different threshold electrical currents of the first bit, which are affected by the size of the electrical barrier, define the various memory states of the memory cell of the multi-level NROM.

Abstract: A method for operating a memory cell of a multi-level NROM is described. The memory cell of the multi-level NROM comprises a nitride layer, wherein the nitride layer comprises a plurality of charge-trapping regions to store locally a plurality of charges as the first bit memory and the second bit of memory. The stored charges of the second bit of memory forms an electrical barrier, which in turns affects the size of the threshold electric current of the first bit. The different threshold electrical currents of the first bit, which are affected by the size of the electrical barrier, define the various memory states of the memory cell of the multi-level NROM.