DUAL DAMASCENE STRUCTURE
A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.
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This is a divisional application of patent application No. 11/162,154, filed on Aug. 31, 2005. The entirety the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a structure of semiconductor device. More particularly, the present invention relates to a dual damascene structure.
2. Description of the Related Art
Currently, dual damascene techniques are widely used to embed metal inter-connect structures in insulating layers. By using dual damascene methods, the overlay errors and the process biases between metal contacts and lines can be reduced, as compared with the conventional method that forms a metal contact first and then directly defines a metal line. Consequently, the reliability and throughput of products can be improved. Hence, dual damascene techniques are very important in advanced semiconductor processes where devices are highly integrated.
In some dual damascene methods, the trench is defined with a hard mask layer with a trench pattern therein, and the contact hole is defined with a patterned photoresist layer with a contact-hole pattern therein that is formed after the hard mask layer. However, when misalignment occurs between the trench pattern and the contact-hole pattern such that the contact-hole pattern exposes a portion of the hard mask layer, the etching step of the contact hole is restricted by the hard mask layer to reduce the cross-sectional area of the contact hole. Therefore, the cross-sectional area of the contact formed later is also reduced, so that the contact resistance is raised to lower the speed of the device or even decrease the yield of the process.
SUMMARY OF THE INVENTIONAccordingly, this invention provides a method for fabricating a dual damascene structure to improve the contact resistance problem due to lithographic misalignment.
This invention also provides a dual damascene structure wherein the contact resistance is less affected by lithographic misalignment.
The method for fabricating a dual damascene structure of this invention is described as follows. A dielectric layer and a hard mask layer are sequentially formed on a substrate, and then a trench pattern is formed in the hard mask layer. A first patterned photoresist layer is formed over the substrate, having a contact-hole pattern therein exposing a portion of the hard mask layer. A pull-back step is performed to pull back the hard mask layer exposed by the contact-hole pattern. The first patterned photoresist layer is used as a mask to remove a portion of the dielectric layer, so as to form an opening in the dielectric layer. After the first patterned photoresist layer is removed, the hard mask layer is used as a mask to etch the dielectric layer down to the substrate, so as to form a contact hole and a trench passing over the contact hole in the dielectric layer. A conductive layer is then formed in the trench and the contact hole.
In one embodiment, the hard mask layer includes a metal hard mask layer, which may include at least one material selected from the group consisting of Ti, TiN, Ta, TaN and WN.
In addition, the hard mask layer may be formed through, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD), and the pull-back step done to the hard mask layer may include a bombardment process with plasma. The dielectric layer may include a low-k material having a dielectric constant lower than 4, while the material of the conductive layer may include copper (Cu).
Moreover, the trench pattern may be formed in the hard mask layer with the following steps, for example. A second patterned photoresist layer having the same trench pattern therein is formed on the hard mask layer, and is then used as a mask to etch the hard mask layer down to the dielectric layer.
The dual damascene structure of this invention can be fabricated based on the above method of this invention. The dual damascene structure includes a substrate, a dielectric layer on the substrate, a hard mask layer on the dielectric layer, a first contact in the dielectric layer, and a conductive line in the hard mask layer and the dielectric layer. The first contact has a horizontal cross-section with an asymmetrically rounded outline, and the conductive line passes over and electrically connects with the first contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the -borders of the laterally swelling portion and the edge portion are contiguous.
Moreover, the above dual damascene structure may further include a second contact between the substrate and the conductive line, the second contact having a horizontal cross-section with a symmetrically rounded outline. The first contact, the second contact and the conductive line may include the same conductive material, such as, copper (Cu).
Since a pull-back step is conducted before the contact-hole etching step to pull back the hard mask layer exposed by the contact-hole pattern of the photoresist layer due to misalignment, the cross-sectional area of the misaligned contact hole is increased, as compared with an equally misaligned contact hole in the prior art. Thus, the contact area between the misaligned contact and the device can be increased to lower the contact resistance, so as to increase the speed of the device as well as to improve the reliability and even the yield of the products.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
Referring to
A hard mask layer 108 is then formed on the dielectric layer 104. The hard mask layer 108 may include a metal hard mask layer, which may be formed from Ti, TiN, Ta, TaN or WN through, for example, CVD or PVD.
In one embodiment, an inorganic insulating layer 106 may be formed on the dielectric layer 104 before the hard mask layer 108 is formed. The material of the inorganic insulating layer 106 may be TEOS-oxide, and the method of forming the same may be CVD. The inorganic insulating layer 106 not only is easier to polish than an organic low-k material, but also can prevent the dielectric layer 104 from being polished and damaged in the CMP process when the latter includes an organic low-k material.
Referring to
Referring to
Ideally, the contact-hole pattern 111 should be aligned with the trench pattern 110, as indicated by dash lines. However, as misalignments occur in the lithography process, the contact-hole pattern 111 will be shifted to expose a portion of the hard mask layer 108. If a contact hole is directly defined using the patterned photoresist layer 114 and the exposed hard mask layer 108 as a mask without a pre-treatment, the contact area between the contact and the device will be much decreased to raise the contact resistance and lower the speed of the device significantly. In view of this problem, this invention provides such a pre-treatment method.
Referring to
Referring to
Referring to
Thereafter, a conductive layer 120 is formed in the trench 110a and the contact holes 11 6a and 118a to form a conductive line 122 and contacts 116b and 118b. Since the inorganic insulating layer 106 and the dielectric layer 104 previously under the edge portion 109 of the exposed hard mask layer 108 are also removed, the conductive line 122 has a laterally swelling portion on an edge portion of the contact 116b, as indicated by the shadow region in
The conductive layer 120 may include copper (Cu) or other metal, and may be formed by, for example, depositing a layer of conductive material over the substrate 100 through CVD and then removing, possibly through CMP, a portion of the conductive material until the hard mask layer 108 is exposed.
It is particularly noted that the above pull-back step can remove an edge portion 109 of the hard mask layer 108 exposed by the patterned photoresist layer 114, so that the size of the misaligned contact hole 116a is increased, as indicated by
The dual damascene structure fabricated with the above method of this invention is described next.
Referring to
The contact 116b is located in the dielectric layer 104. In this embodiment, the dual damascene structure may further include a contact 118b between the substrate 100 and the conductive line 122 and near the contact 116b.
Though both of the contacts 116b and 118b are misaligned with the conductive line 122, the contact 118b is different from the contact 116b for it is defined without overlapping with the hard mask layer 108, as shown in
Accordingly, in the method for fabricating a dual damascene structure of this invention, the pull-back step done to the exposed hard mask layer 108 can increase the horizontal cross-sectional area of the misaligned contact 116b, while the increased area is indicated by the shadow region in
Though the above embodiment is described with misalignment in X-direction of
According to the above embodiment of this invention, since a pull-back step is conducted before the contact-hole etching step to pull back the hard mask layer exposed by the contact-hole pattern of the photoresist layer due to misalignment, the cross-sectional area of the misaligned contact hole can be increased. Thus, the contact area between the misaligned contact and the device can be increased to lower the contact resistance, so as to increase the speed of the device as well as to improve the reliability and even the yield of the products.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims
1. A dual damascene structure, comprising:
- a substrate;
- a dielectric layer on the substrate;
- a hard mask layer on the dielectric layer;
- a first contact in the dielectric layer, having a horizontal cross-section with an asymmetrically rounded outline; and
- a conductive line in the hard mask layer and the dielectric layer, passing over and electrically connecting with the first contact,
- wherein the conductive line has a laterally swelling portion on an edge portion of the first contact, and borders of the laterally swelling portion and the edge portion are contiguous.
2. The dual damascene structure of claim 1, wherein the hard mask layer comprises a metal hard mask layer.
3. The dual damascene structure of claim 2, wherein the metal hard mask layer comprises at least one material selected from the group consisting of Ti, TiN, Ta, TaN and WN.
4. The dual damascene structure of claim 1, further comprising:
- a second contact between the substrate and the conductive line, having a horizontal cross-section with a symmetrically rounded outline.
5. The dual damascene structure of claim 4, wherein the first contact, the second contact and the conductive layer comprise the same conductive material.
6. The dual damascene structure of claim 5, wherein the conductive material comprises copper (Cu).
7. The dual damascene structure of claim 1, wherein the dielectric layer comprises a low-k material having a dielectric constant lower than 4.
Type: Application
Filed: Dec 8, 2006
Publication Date: Apr 12, 2007
Applicant: UNITED MICROELECTRONICS CORP. (Hsinchu)
Inventors: Jen-Ren Huang (Tainan County), Cheng-Ming Weng (Hsinchu County), Miao-Chun Lin (Tainan County)
Application Number: 11/608,252
International Classification: H01L 29/94 (20060101); H01L 27/108 (20060101); H01L 29/76 (20060101); H01L 31/119 (20060101);