Patents by Inventor Jen-Sheng Yang
Jen-Sheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200098828Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a memory device over a substrate and forming an inter-level dielectric (ILD) layer over the memory device. The ILD layer is selectively etched to define a first cavity that exposes a top of the memory device and to define a second cavity that is laterally separated from the first cavity by the ILD layer. The second cavity is defined by a smooth sidewall of the ILD layer that extends between upper and lower surfaces of the ILD layer. A conductive material is formed within the first cavity and the second cavity.Type: ApplicationFiled: November 26, 2019Publication date: March 26, 2020Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
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Patent number: 10566387Abstract: The present disclosure relates to a method of forming an integrated circuit. In some embodiments, the method may be performed by forming a lower interconnect structure within a first inter-level dielectric (ILD) layer over an upper surface of a substrate, and forming a resistive random access memory (RRAM) device over the lower interconnect structure. A second ILD layer is formed over the RRAM device. The second ILD layer is patterned to remove a part of the second ILD layer that defines a cavity. The cavity vertically extends from an upper surface of the second ILD layer to an upper surface of the RRAM device and laterally extends past opposing sidewalls of the RRAM device. An upper interconnect wire is formed within the cavity.Type: GrantFiled: August 22, 2018Date of Patent: February 18, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
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Patent number: 10566519Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.Type: GrantFiled: November 27, 2017Date of Patent: February 18, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
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Publication number: 20200020745Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit has a first inter-level dielectric (ILD) layer over a substrate. A lower electrode is over the first ILD layer, a data storage structure is over the lower electrode, and an upper electrode is over the data storage structure. An upper interconnect wire directly contacts an entirety of an upper surface of the upper electrode. A conductive via directly contacts an upper surface of the upper interconnect wire. The conductive via has an outermost sidewall that is directly over the upper surface of the upper interconnect wire.Type: ApplicationFiled: September 22, 2019Publication date: January 16, 2020Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
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Publication number: 20190386204Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.Type: ApplicationFiled: August 27, 2019Publication date: December 19, 2019Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
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Publication number: 20190341263Abstract: A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
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Publication number: 20190272873Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.Type: ApplicationFiled: May 16, 2019Publication date: September 5, 2019Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Patent number: 10388531Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.Type: GrantFiled: September 27, 2017Date of Patent: August 20, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
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Patent number: 10311952Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.Type: GrantFiled: March 27, 2018Date of Patent: June 4, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Publication number: 20190103493Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.Type: ApplicationFiled: November 30, 2018Publication date: April 4, 2019Inventors: Kuo-Chi TU, Jen-Sheng YANG, Sheng-Hung SHIH, Tong-Chern ONG, Wen-Ting CHU
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Patent number: 10249756Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.Type: GrantFiled: June 30, 2017Date of Patent: April 2, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chi Tu, Jen-Sheng Yang, Sheng-Hung Shih, Tong-Chern Ong, Wen-Ting Chu
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Publication number: 20190058109Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.Type: ApplicationFiled: November 27, 2017Publication date: February 21, 2019Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
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Publication number: 20180374901Abstract: The present disclosure relates to a method of forming an integrated circuit. In some embodiments, the method may be performed by forming a lower interconnect structure within a first inter-level dielectric (ILD) layer over an upper surface of a substrate, and forming a resistive random access memory (RRAM) device over the lower interconnect structure. A second ILD layer is formed over the RRAM device. The second ILD layer is patterned to remove a part of the second ILD layer that defines a cavity. The cavity vertically extends from an upper surface of the second ILD layer to an upper surface of the RRAM device and laterally extends past opposing sidewalls of the RRAM device. An upper interconnect wire is formed within the cavity.Type: ApplicationFiled: August 22, 2018Publication date: December 27, 2018Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
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Patent number: 10164185Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage.Type: GrantFiled: September 12, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Hung Shih, Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
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Patent number: 10163981Abstract: The present disclosure relates to an integrated circuit having an interconnect wire contacting an upper electrode of the RRAM (resistive random access memory) device, and a method of formation. In some embodiments, the integrated circuit comprises an RRAM device having a dielectric data storage layer disposed between a lower electrode and an upper electrode. An interconnect wire contacts an upper surface of the upper electrode, and an interconnect via is arranged onto the interconnect wire. The interconnect via is set back from one or more outermost sidewalls of the interconnect wire. The interconnect wire has a relatively large size that provides for a good electrical connection between the interconnect wire and the upper electrode, thereby increasing a process window of the RRAM device.Type: GrantFiled: February 24, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
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Patent number: 10164094Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.Type: GrantFiled: June 30, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chi Tu, Jen-Sheng Yang, Sheng-Hung Shih, Tong-Chern Ong, Wen-Ting Chu
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Patent number: 10158072Abstract: A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.Type: GrantFiled: July 28, 2017Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jen-Sheng Yang, Wen-Ting Chu, Chih-Yang Chang, Chin-Chieh Yang, Kuo-Chi Tu, Sheng-Hung Shih, Yu-Wen Liao, Hsia-Wei Chen, I-Ching Chen
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Publication number: 20180351099Abstract: A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.Type: ApplicationFiled: July 28, 2017Publication date: December 6, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jen-Sheng YANG, Wen-Ting CHU, Chih-Yang CHANG, Chin-Chieh YANG, Kuo-Chi TU, Sheng-Hung SHIH, Yu-Wen LIAO, Hsia-Wei CHEN, I-Ching CHEN
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Patent number: 10109793Abstract: The present disclosure relates to a memory cell having a multi-layer bottom electrode with an insulating core that provides for good gap fill ability, and an associated method of formation. In some embodiments, the memory cell includes a bottom electrode having an insulating material surrounded by a conductive material. A dielectric data storage layer is arranged over the bottom electrode, and a top electrode is arranged over the dielectric data storage layer.Type: GrantFiled: September 26, 2016Date of Patent: October 23, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
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Publication number: 20180218770Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.Type: ApplicationFiled: March 27, 2018Publication date: August 2, 2018Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen