Patents by Inventor Jen Shu
Jen Shu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10075161Abstract: A method and a device for preventing inadvertently touch of an electronic device are provided, the method includes: receiving an operating motion by a button switch; determining whether the button switch is triggered by receiving the operating motion; determining whether a human body is closing to the button switch; if the human body is closing to the button switch and the button switch is triggered, sending a button switch signal corresponding to the button switch to the electronic device to perform a function corresponding to the button switch.Type: GrantFiled: January 10, 2014Date of Patent: September 11, 2018Assignee: Wistron CorporationInventor: Chia-Jen Shu
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Patent number: 9983662Abstract: An electronic device including a physical button, a processing unit and a sensing unit is provided. The processing unit is coupled to the physical button and the sensing unit is coupled to the processing unit. When the electronic device enters a hibernation mode or in a shutdown state, the sensing unit continuously detects a wake-up signal. When receiving the wake-up signal, the sensing unit wakes up the processing unit. The sensing unit further receives an instruction signal externally, generates an instruction information according to the instruction signal, and sends the instruction information to the processing unit. When receiving the instruction information, the processing unit adjusts a corresponding function of the physical button according to the instruction information.Type: GrantFiled: January 3, 2014Date of Patent: May 29, 2018Assignee: Wistron CorporationInventors: Yung-Yen Chang, Chia-Jen Shu
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Patent number: 9184333Abstract: A fabrication line includes a texturizing module configured to texture a substrate, an emitter module configured to form an emitter region, a passivation layer module configured to form a passivation layer, a barrier contact module configured to form a barrier contact region, a firing module configured to anneal the barrier contact region, a top metal contact module configured to form a top metal contact region, and a soldering module configured to solder the barrier contact region to the top metal contact region. The modules are integrated by one or more automated substrate handlers into a single fabrication line. A method for fabricating a solar cell includes sequentially, in an automated fabrication line: doping a dopant in a substrate; disposing a passivation layer; disposing and annealing a barrier metal paste to form a barrier contact; and disposing and annealing a metal contact paste to form a top metal contact region.Type: GrantFiled: March 8, 2013Date of Patent: November 10, 2015Assignee: APPLIED MATERIALS, INC.Inventors: Suketu Arun Parikh, Jen Shu, James M. Gee
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Publication number: 20150088278Abstract: An electronic device including a physical button, a processing unit and a sensing unit is provided. The processing unit is coupled to the physical button and the sensing unit is coupled to the processing unit. When the electronic device enters a hibernation mode or in a shutdown state, the sensing unit continuously detects a wake-up signal. When receiving the wake-up signal, the sensing unit wakes up the processing unit. The sensing unit further receives an instruction signal externally, generates an instruction information according to the instruction signal, and sends the instruction information to the processing unit. When receiving the instruction information, the processing unit adjusts a corresponding function of the physical button according to the instruction information.Type: ApplicationFiled: January 3, 2014Publication date: March 26, 2015Applicant: Wistron CorporationInventors: Yung-Yen Chang, Chia-Jen Shu
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Publication number: 20150084436Abstract: A method and a device for preventing inadvertently touch of an electronic device are provided, the method includes: receiving an operating motion by a button switch; determining whether the button switch is triggered by receiving the operating motion; determining whether a human body is closing to the button switch; if the human body is closing to the button switch and the button switch is triggered, sending a button switch signal corresponding to the button switch to the electronic device to perform a function corresponding to the button switch.Type: ApplicationFiled: January 10, 2014Publication date: March 26, 2015Applicant: Wistron CorporationInventor: Chia-Jen Shu
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Publication number: 20130288424Abstract: A fabrication line includes a texturizing module configured to texture a substrate, an emitter module configured to form an emitter region, a passivation layer module configured to form a passivation layer, a barrier contact module configured to form a barrier contact region, a firing module configured to anneal the barrier contact region, a top metal contact module configured to form a top metal contact region, and a soldering module configured to solder the barrier contact region to the top metal contact region. The modules are integrated by one or more automated substrate handlers into a single fabrication line. A method for fabricating a solar cell includes sequentially, in an automated fabrication line: doping a dopant in a substrate; disposing a passivation layer; disposing and annealing a barrier metal paste to form a barrier contact; and disposing and annealing a metal contact paste to form a top metal contact region.Type: ApplicationFiled: March 8, 2013Publication date: October 31, 2013Inventors: Suketu Arun PARIKH, Jen SHU, James M. GEE
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Patent number: 8293460Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.Type: GrantFiled: December 19, 2008Date of Patent: October 23, 2012Assignee: Applied Materials, Inc.Inventors: Hui W. Chen, Chorng-Ping Chang, Yongmei Chen, Huixiong Dai, Jiahua Yu, Susie X. Yang, Xumou Xu, Christopher D. Bencher, Raymond Hoiman Hung, Michael P. Duane, Christopher Siu Wing Ngai, Jen Shu, Kenneth MacWilliams
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Patent number: 8268728Abstract: The present invention generally provides a method of forming a high efficiency solar cell device by preparing a surface and/or forming at least a part of a high quality passivation layer on a silicon containing substrate. Embodiments of the present invention may be especially useful for preparing a surface of a p-type doped region formed on a silicon substrate so that a high quality passivation layer can be formed thereon. In one embodiment, the methods include exposing a surface of the solar cell substrate to a plasma to clean and modify the physical, chemical and/or electrical characteristics of the surface.Type: GrantFiled: August 2, 2011Date of Patent: September 18, 2012Assignee: Applied Materials, Inc.Inventors: Michael P. Stewart, Lisong Zhou, Jen Shu, Li (Sherry) Xu
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Patent number: 8084310Abstract: Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density.Type: GrantFiled: October 21, 2009Date of Patent: December 27, 2011Assignee: Applied Materials, Inc.Inventors: Bencherki Mebarki, Li Yan Miao, Christopher Dennis Bencher, Jen Shu
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Publication number: 20110287577Abstract: The present invention generally provides a method of forming a high efficiency solar cell device by preparing a surface and/or forming at least a part of a high quality passivation layer on a silicon containing substrate. Embodiments of the present invention may be especially useful for preparing a surface of a p-type doped region formed on a silicon substrate so that a high quality passivation layer can be formed thereon. In one embodiment, the methods include exposing a surface of the solar cell substrate to a plasma to clean and modify the physical, chemical and/or electrical characteristics of the surface.Type: ApplicationFiled: August 2, 2011Publication date: November 24, 2011Applicant: Applied Materials, Inc.Inventors: Michael P. STEWART, Lisong Zhou, Jen Shu, Li (Sherry) Xu
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Patent number: 8008208Abstract: The present invention generally provides a method of forming a high efficiency solar cell device by preparing a surface and/or forming at least a part of a high quality passivation layer on a silicon containing substrate. Embodiments of the present invention may be especially useful for preparing a surface of a p-type doped region formed on a silicon substrate so that a high quality passivation layer can be formed thereon. In one embodiment, the methods include exposing a surface of the solar cell substrate to a plasma to clean and modify the physical, chemical and/or electrical characteristics of the surface.Type: GrantFiled: December 7, 2010Date of Patent: August 30, 2011Assignee: Applied Materials, Inc.Inventors: Michael P. Stewart, Lisong Zhou, Jen Shu, Li (Sherry) Xu
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Publication number: 20110136286Abstract: The present invention generally provides a method of forming a high efficiency solar cell device by preparing a surface and/or forming at least a part of a high quality passivation layer on a silicon containing substrate. Embodiments of the present invention may be especially useful for preparing a surface of a p-type doped region formed on a silicon substrate so that a high quality passivation layer can be formed thereon. In one embodiment, the methods include exposing a surface of the solar cell substrate to a plasma to clean and modify the physical, chemical and/or electrical characteristics of the surface.Type: ApplicationFiled: December 7, 2010Publication date: June 9, 2011Applicant: Applied Materials, Inc.Inventors: Michael P. Stewart, Lisong Zhou, Jen Shu, Li (Sherry) Xu
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Publication number: 20100136792Abstract: Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density.Type: ApplicationFiled: October 21, 2009Publication date: June 3, 2010Applicant: Applied Materials, Inc.Inventors: Bencherki Mebarki, Li Yan Miao, Christopher Dennis Bencher, Jen Shu
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Publication number: 20090311635Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.Type: ApplicationFiled: December 19, 2008Publication date: December 17, 2009Inventors: HUI W. CHEN, CHORNG-PING CHANG, YONGMEI CHEN, HUIXIONG DAI, JIAHUA YU, SUSIE X. YANG, XUMOU XU, CHRISTOPHER D. BENCHER, RAYMOND HOIMAN HUNG, MICHAEL P. DUANE, CHRISTOPHER SIU WING NGAI, JEN SHU, KENNETH MACWILLIAMS
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Patent number: 6632478Abstract: An embodiment of the present invention provides methods for forming a carbon-containing layer having a low dielectric constant and good gap-fill capabilities. A method includes depositing a carbon-containing layer on a substrate and transforming the carbon-containing layer to remove at least some of the carbon. The transforming step may include annealing the carbon-containing layer in a furnace containing a hydrogen atmosphere, for example. The carbon-containing layer may be a carbon-doped silicon oxide material, where the transforming step changes the carbon-doped silicon oxide. Additionally, the method may include subjecting the annealed layer to a hydrogen and/or low oxygen plasma treatment to further remove carbon from the layer. Additionally, a step of adding a capping layer to the annealed, plasma treated material is provided.Type: GrantFiled: February 22, 2001Date of Patent: October 14, 2003Assignee: Applied Materials, Inc.Inventors: Frederic Gaillard, Li-Qun Xia, Jen Shu, Ellie Yieh, Tian-Hoe Lim
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Patent number: 6593615Abstract: Substrate bombardment during HDP deposition of carbon-doped silicon oxide film results in filling the gaps between metal lines with carbon-doped low k dielectric material. This leads to the placement of low k dielectric between the narrow metal lines while the films over the metal lines have higher dielectric constant due to removal of carbon from these films during ion bombardment. Films over the metal lines have properties similar to silicon dioxide and are ready for sequential integration processes.Type: GrantFiled: October 18, 2001Date of Patent: July 15, 2003Assignee: National Semiconductor CorporationInventors: Jen Shu, Michael E. Thomas
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Patent number: 6576345Abstract: Thin films possessing low dielectric constants (e.g., dielectric constants below 3.0) are formed on integrated circuits or other substrates. Caged-siloxane precursors are linked in such a way as to form dielectric layers, which exhibit low dielectric constants by virtue of their silicon dioxide-like molecular structure and porous nature. Supercritical fluids may be used as the reaction medium and developer both to the dissolve and deliver the caged-siloxane precursors and to remove reagents and byproducts from the reaction chamber and resultant porous film created.Type: GrantFiled: November 30, 2000Date of Patent: June 10, 2003Inventors: Patrick A. Van Cleemput, Ravi Kumar Laxman, Jen Shu, Michelle T. Schulberg, Bunsen Nie
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Publication number: 20020164429Abstract: An embodiment of the present invention provides methods for forming a carbon-containing layer having a low dielectric constant and good gap-fill capabilities. A method includes depositing a carbon-containing layer on a substrate and transforming the carbon-containing layer to remove at least some of the carbon. The transforming step may include annealing the carbon-containing layer in a furnace containing a hydrogen atmosphere, for example. The carbon-containing layer may be a carbon-doped silicon oxide material, where the transforming step changes the carbon-doped silicon oxide. Additionally, the method may include subjecting the annealed layer to a hydrogen and/or low oxygen plasma treatment to further remove carbon from the layer. Additionally, a step of adding a capping layer to the annealed, plasma treated material is provided.Type: ApplicationFiled: February 22, 2001Publication date: November 7, 2002Applicant: Applied Materials, Inc.Inventors: Frederic Gaillard, Li-Qun Xia, Jen Shu, Ellie Yieh, Tian-Hoe Lim
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Patent number: 6433575Abstract: A cathode-anode apparatus is constructed whereby the wafer under test, connected to a conducting wire, forms the cathode terminal and a copper plate, also connected to a conducting wire, forms the anode terminal. The wafer under test and the copper plate are immersed in a CuSO4—H2O solution. A positive dc voltage is applied to the copper plate; the dc current ionizes the CuSO4 solution and forms Cu2+ ions. These Cu2+ ions will diffuse to the wafer surface. Most of the Cu2+ ions will accumulate in and around defective contacts or vias in the semiconductor surface making these defective contacts or vias readily identifiable.Type: GrantFiled: March 13, 2001Date of Patent: August 13, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ming-Chun Chou, Huai-Jen Shu
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Patent number: 6383933Abstract: A planarization process in which an organic film prevents oxide dishing during the chemical mechanical polishing step. In the planarization process an organic film having high CMP selectivity to silicon dioxide is spun over silicon dioxide. A patterned mask is then placed over the organic film and the exposed portions of the organic film are etched away. The remaining portions of the organic film prevent oxide dishing during chemical mechanical polishing because the high CMP selectivity of the organic film to silicon dioxide stops the etching before oxide dishing occurs. The organic film may then be oxygen ashed off the planarized surface if so desired.Type: GrantFiled: March 23, 2000Date of Patent: May 7, 2002Assignee: National Semiconductor CorporationInventors: Jen Shu, Michael E. Thomas, Prochy Sethna