Patents by Inventor Jen-Yu Wang
Jen-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10651235Abstract: A first MRAM set includes a first transistor and a second transistor. The first transistor includes a first gate structure, a first source/drain doping region and a first common source/drain doping region. The second transistor includes a second gate structure, a second source/drain doping region and the first common source/drain doping region. A second MTJ is disposed on the second transistor. The first common source/drain doping region electrically connects to the second MTJ. A first MTJ is disposed on the first transistor. The sizes of the first MTJ and the second MTJ are different. The second MTJ connects to the first MTJ in series. A bit line electrically connects the first MTJ. A source line electrically connects to the first source/drain doping region and the second source/drain doping region.Type: GrantFiled: March 8, 2019Date of Patent: May 12, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Ting Wu, Jhen-Siang Wu, Po-Chun Yang, Yung-Ching Hsieh, Zong-Sheng Zheng, Jian-Jhong Chen, Jen-Yu Wang, Cheng-Tung Huang
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Publication number: 20200091034Abstract: A semiconductor package is provided. The semiconductor package includes a substrate and a semiconductor die over the substrate. A heat-dissipating feature covers the substrate and the semiconductor die, and a composite thermal interface material (TIM) structure is thermally bonded between the semiconductor die and the heat-dissipating feature. The composite TIM structure includes a metal-containing matrix material layer and polymer particles embedded in the metal-containing matrix material layer.Type: ApplicationFiled: May 22, 2019Publication date: March 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tung-Liang SHAO, Jen-Yu WANG, Chung-Jung WU, Chih-Hang TUNG, Chen-Hua YU
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Publication number: 20200035680Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.Type: ApplicationFiled: October 6, 2019Publication date: January 30, 2020Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
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Patent number: 10483264Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.Type: GrantFiled: July 27, 2017Date of Patent: November 19, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
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Publication number: 20190006360Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.Type: ApplicationFiled: July 27, 2017Publication date: January 3, 2019Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
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Patent number: 10056463Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.Type: GrantFiled: June 20, 2017Date of Patent: August 21, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Su Xing, Hsueh-Wen Wang, Chien-Yu Ko, Yu-Cheng Tung, Jen-Yu Wang, Cheng-Tung Huang, Yu-Ming Lin
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Publication number: 20180006129Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.Type: ApplicationFiled: June 20, 2017Publication date: January 4, 2018Inventors: Su Xing, Hsueh-Wen Wang, Chien-Yu Ko, Yu-Cheng Tung, Jen-Yu Wang, Cheng-Tung Huang, Yu-Ming Lin
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Patent number: 9793296Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.Type: GrantFiled: October 17, 2016Date of Patent: October 17, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Yin Weng, Cheng-Tung Huang, Ya-Ru Yang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
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Patent number: 9722093Abstract: An oxide semiconductor transistor includes an oxide semiconductor channel layer, a metal gate, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The metal gate is disposed on the oxide semiconductor channel layer. The gate insulation layer is disposed between the metal gate and the oxide semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the metal gate. The ferroelectric material layer is disposed between the internal electrode and the metal gate. The ferroelectric material layer in the oxide semiconductor transistor of the present invention is used to enhance the electrical characteristics of the oxide semiconductor transistor.Type: GrantFiled: September 1, 2016Date of Patent: August 1, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Su Xing, Hsueh-Wen Wang, Chien-Yu Ko, Yu-Cheng Tung, Jen-Yu Wang, Cheng-Tung Huang, Yu-Ming Lin
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Publication number: 20170040346Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.Type: ApplicationFiled: October 17, 2016Publication date: February 9, 2017Inventors: Wen-Yin Weng, Cheng-Tung Huang, Ya-Ru Yang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
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Patent number: 9508799Abstract: A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.Type: GrantFiled: August 26, 2014Date of Patent: November 29, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Yin Weng, Cheng-Tung Huang, Ya-Ru Yang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
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Patent number: 9312600Abstract: A stylus includes a conductive rod, a circuit board, and an antenna. The conductive rod has a first opening. The circuit board is disposed in the conductive rod and includes a ground portion, wherein the conductive rod is electrically connected to the ground portion. The antenna includes a radiating portion and a feeding portion. The feeding portion is electrically connected to the circuit board and extends to the outside of the conductive rod via the first opening. The radiating portion is disposed at the outside of the conductive rod and is electrically connected to the feeding portion.Type: GrantFiled: February 25, 2013Date of Patent: April 12, 2016Assignee: ASUSTeK COMPUTER INC.Inventors: Jen-Yu Wang, Wei-Cheng Lo, Yu-Chia Chang, Meng-Huan Wu, Chia-Hao Chang
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Patent number: 9299839Abstract: A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above.Type: GrantFiled: October 3, 2014Date of Patent: March 29, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
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Publication number: 20160064485Abstract: A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.Type: ApplicationFiled: August 26, 2014Publication date: March 3, 2016Inventors: Wen-Yin Weng, Cheng-Tung Huang, Ya-Ru Yang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
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Publication number: 20160064563Abstract: A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above.Type: ApplicationFiled: October 3, 2014Publication date: March 3, 2016Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: WEN-YIN WENG, CHENG-TUNG HUANG, WEI-HENG HSU, YI-TING WU, YU-MING LIN, JEN-YU WANG
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Publication number: 20160003888Abstract: A method of characterizing a device may be used to determine a metal work function of the device according to a threshold voltage, a body effect, and an oxide capacitance of the device. The threshold voltage may be determined according to a current to voltage curve. The oxide capacitance may be determined according to a capacitor to voltage curve.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Inventors: Wen-Yin Weng, Wei-Heng Hsu, Cheng-Tung Huang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
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Publication number: 20130234998Abstract: A stylus includes a conductive rod, a circuit board, and an antenna. The conductive rod has a first opening. The circuit board is disposed in the conductive rod and includes a ground portion, wherein the conductive rod is electrically connected to the ground portion. The antenna includes a radiating portion and a feeding portion. The feeding portion is electrically connected to the circuit board and extends to the outside of the conductive rod via the first opening. The radiating portion is disposed at the outside of the conductive rod and is electrically connected to the feeding portion.Type: ApplicationFiled: February 25, 2013Publication date: September 12, 2013Applicant: ASUSTeK COMPUTER INC.Inventors: Jen-Yu Wang, Wei-Cheng Lo, Yu-Chia Chang, Meng-Huan Wu, Chia-Hao Chang
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Patent number: 7800903Abstract: A heat-dissipating structure includes a support unit and a fan unit disposed in the receiving space. The support unit has a plane portion, a support portion extending downwards from a front side of the plane portion, and an opening passing through the plane portion. The plane portion has a board body, a concave space formed on the top surface of the plane portion, a non-skid pad detachably received in the concave space, a slender block body disposed on a base of the top surface of the board body, and a slender non-skid body disposed on a base of the bottom surface of the board body. The support portion has a support body, a receiving space formed in its inside, a plurality of slender openings formed on two opposite lateral sides of the support body, and a slender non-skid body disposed on a base of the support body.Type: GrantFiled: September 30, 2008Date of Patent: September 21, 2010Assignee: Cooler Master Co., Ltd.Inventor: Jen-Yu Wang
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Publication number: 20100079945Abstract: A heat-dissipating structure includes a support unit and a fan unit disposed in the receiving space. The support unit has a plane portion, a support portion extending downwards from a front side of the plane portion, and an opening passing through the plane portion. The plane portion has a board body, a concave space formed on the top surface of the plane portion, a non-skid pad detachably received in the concave space, a slender block body disposed on a base of the top surface of the board body, and a slender non-skid body disposed on a base of the bottom surface of the board body. The support portion has a support body, a receiving space formed in its inside, a plurality of slender openings formed on two opposite lateral sides of the support body, and a slender non-skid body disposed on a base of the support body.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventor: Jen-Yu Wang
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Publication number: 20080084146Abstract: A media-storing fixed frame, a computer casing and a computer host are disclosed. The computer host includes a host frame, a media-storing reader, and an operation panel. The media-storing reader is fixed in the host frame, and the media-storing reader having a setting direction relative to the host frame is changeable. The operation panel is detachably fixed on an outside portion of the host frame, and the operation panel defines a referring direction that is changeable. When the computer host is vertical or horizontal, a setting direction of the media-storing reader and a setting direction of the operation panel are changeable according to user's operation habit.Type: ApplicationFiled: September 28, 2007Publication date: April 10, 2008Inventor: Jen-Yu Wang