Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.

Abstract: Techniques regarding selectively tuning the operating frequency of superconducting Josephson junction resonators are provided. For example, one or more embodiments described herein can comprise a method that can include chemically altering a Josephson junction of a Josephson junction resonator via a plasma treatment. The method can also comprise selectively tuning an operating frequency of the Josephson junction resonator based on a property of the plasma treatment.

Abstract: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.

Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.

Abstract: A semiconductor device or circuit includes a vertical bipolar junction transistor (vBJT) and a vertical filed effect transistor (vFET). The vBJT collector is electrically and/or physically connected to an adjacent vFET source. For example, a vBJT collector and a vFET source may be integrated upon a same semiconductor material substrate or layer. The vFET provides negative feedback for the collector-base voltage and the vBJT emitter and collector allow for low transit times.

Abstract: A double Dolan Bridge structure includes two Dolan Bridges arranged side-by-side to form a Josephson Junction. Each Dolan Bridge includes a substrate, and a triple stack resist configuration including three layers of material arranged on the substrate. An asymmetrically arranged junction including at least three metallic layers is arranged on the substrate in a stack having no more than two of the least three metallic stacked on each other.

Abstract: A semiconductor device or circuit includes a vertical bipolar junction transistor (vBJT) and a vertical filed effect transistor (vFET). The vBJT collector is electrically and/or physically connected to an adjacent vFET source. For example, a vBJT collector and a vFET source may be integrated upon a same semiconductor material substrate or layer. The vFET provides negative feedback for the collector-base voltage and the vBJT emitter and collector allow for low transit times.

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.

Abstract: A method of measuring contact resistance at an interface for superconducting circuits is provided. The method includes using a chain structure of superconductors to measure a contact resistance at a contact between contacting superconductor. The method further includes eliminating ohmic resistance from wire lengths in the chain structure by operating below the lowest superconducting transition temperature of all the superconductors in the chain structure. The measurement is dominated by contact resistances of the contacts between contacting superconductors in the chain.

Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, and forming a bottom source/drain region adjacent a base of the fin. In the method, a dielectric layer, a work function metal layer and a first gate metal layer are sequentially deposited on the bottom source/drain region and around the fin. The dielectric layer, the work function metal layer and the first gate metal layer form a gate structure. The method also includes removing the dielectric layer, the work function metal layer and the first gate metal layer from an end portion of the fin, and depositing a second gate metal layer around the end portion of the fin in place of the removed dielectric layer, the removed work function metal layer and the removed first gate metal layer. The second gate metal layer contacts the end portion of the fin.

Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate protection of a substrate in a qubit device using sacrificial material are provided. According to an embodiment, a device can comprise a superconducting lead provided on a pillar of a sacrificial material provided on a substrate. The device can further comprise a collapsed superconducting junction provided on the substrate and coupled to the superconducting lead.

Abstract: A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.

Abstract: A method of measuring contact resistance at an interface for superconducting circuits is provided. The method includes using a chain structure of superconductors to measure a contact resistance at a contact between contacting superconductor. The method further includes eliminating ohmic resistance from wire lengths in the chain structure by operating below the lowest superconducting transition temperature of all the superconductors in the chain structure. The measurement is dominated by contact resistances of the contacts between contacting superconductors in the chain.

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

Abstract: Techniques regarding selectively tuning the operating frequency of superconducting Josephson junction resonators are provided. For example, one or more embodiments described herein can comprise a method that can include chemically altering a Josephson junction of a Josephson junction resonator via a plasma treatment. The method can also comprise selectively tuning an operating frequency of the Josephson junction resonator based on a property of the plasma treatment.

Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

Abstract: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.