Patents by Inventor Jeng-Bang Yau

Jeng-Bang Yau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10957707
    Abstract: The dosimeter has two vertical field effect transistors (VFETs), each VFET with a bottom and top source/drain and channel between them. An implanted charge storage region material lies between and in contact with each of the vertical channels. A trapped charge is within the implanted charge storage region. The amount of the trapped charge is related to an amount of radiation that passes through the implanted charge storage region.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jeng-Bang Yau, Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Publication number: 20210083139
    Abstract: A semiconductor radiation monitor (i.e., dosimeter) is provided that has an oxide charge storage region located on a first side of a semiconductor fin and a functional gate structure located on a second side of the semiconductor fin that is opposite the first side. Charges are created in the oxide charge storage region that is located on the first side of the semiconductor fin and detected on the second side of the semiconductor fin by the functional gate structure. Multiple semiconductor fins in parallel can form a dense and very sensitive semiconductor radiation monitor.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Jeng-Bang Yau, Karthik Balakrishnan
  • Patent number: 10937898
    Abstract: A structure and method of forming a lateral bipolar junction transistor (LBJT) that includes: a first base layer, a second base layer over the first base layer, and an emitter region and collector region present on opposing sides of the first base layer, where the first base layer has a wider-band gap than the second base layer, and where the first base layer includes a III-V semiconductor material.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek, Karthik Balakrishnan, Jeng-Bang Yau
  • Patent number: 10916537
    Abstract: An electric static discharge (ESD) diode pair is disclosed. The first diode of the device includes a first diode junction portion having vertically orientated and horizontally oriented portions of a first conductivity and a second diode junction portion of a second conductivity in direct contact with both of the vertically orientated and horizontally orientated portions of the first diode junction portion. The second diode of the device includes a first diode junction portion having vertically orientated and horizontally oriented portions of a second conductivity and a second diode junction portion having a first conductivity in direct contact with both of the vertically orientated and horizontally orientated portions of the first diode junction portion. A common electrical contact is in direct contact first diode junction portion for each of the first diode and the second diode.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 10916651
    Abstract: A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Tak H. Ning, Jeng-Bang Yau, Bahman Hekmatshoartabari
  • Patent number: 10916629
    Abstract: A semiconductor structure that occupies only one areal device area is provided that includes a charge storage region sandwiched between a pFET nanosheet device and an nFET nanosheet device. The charge storage region is an epitaxial oxide nanosheet that is lattice matched to an underlying first silicon channel material nanosheet and an overlying second silicon channel material nanosheet. The semiconductor structure can be used as an EPROM device.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Jeng-Bang Yau, Tak H. Ning, Ghavam G. Shahidi
  • Publication number: 20210028138
    Abstract: In an embodiment, a method for forming a solder bump includes preparing a transfer mold having a solder pillar extending from a mold substrate and through a first photoresist layer and having a shape partially defined by a second photoresist layer that is removed prior to transfer of the solder. In an embodiment, the mold substrate is flexible. In an embodiment, the transfer mold is flexible. In an embodiment, the method includes providing a device substrate having a wettable pad. In an embodiment, the method includes placing the transfer mold and the device substrate into aligned contact such that the solder pillar is in contact with the wettable pad. In an embodiment, the method includes forming a metallic bond between the solder pillar and the wettable pad. In an embodiment, the method includes removing the mold substrate and first photoresist layer.
    Type: Application
    Filed: August 11, 2020
    Publication date: January 28, 2021
    Applicant: International Business Machines Corporation
    Inventors: Eric Peter Lewandowski, Jae-Woong Nah, Jeng-Bang Yau, Peter Jerome Sorce
  • Patent number: 10900952
    Abstract: A biosensor includes a bulk silicon substrate and a vertical bipolar junction transistor (BJT) formed on at least a portion of the substrate. The BJT includes an emitter region, a collector region and an epitaxially grown intrinsic base region between the emitter and collector regions. The biosensor further includes a sensing structure formed on at least a portion of two vertical surfaces of the intrinsic base region of the BJT. The sensing structure includes a channel/trench opening, exposing the intrinsic base region on at least first and second opposing sides thereof, and at least one dielectric layer formed in the channel/trench opening and contacting at least a portion of the intrinsic base region, the dielectric layer being configured to respond to charges in biological molecules.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Jeng-Bang Yau, Bahman Hekmatshoartabari
  • Patent number: 10896971
    Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, and forming a bottom source/drain region adjacent a base of the fin. In the method, a dielectric layer, a work function metal layer and a first gate metal layer are sequentially deposited on the bottom source/drain region and around the fin. The dielectric layer, the work function metal layer and the first gate metal layer form a gate structure. The method also includes removing the dielectric layer, the work function metal layer and the first gate metal layer from an end portion of the fin, and depositing a second gate metal layer around the end portion of the fin in place of the removed dielectric layer, the removed work function metal layer and the removed first gate metal layer. The second gate metal layer contacts the end portion of the fin.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Tak H. Ning, Bahman Hekmatshoartabari, Jeng-Bang Yau
  • Patent number: 10879202
    Abstract: In an embodiment, a method for forming a solder bump includes preparing a transfer mold having a solder pillar extending from a mold substrate and through a first photoresist layer and having a shape partially defined by a second photoresist layer that is removed prior to transfer of the solder. In an embodiment, the mold substrate is flexible. In an embodiment, the transfer mold is flexible. In an embodiment, the method includes providing a device substrate having a wettable pad. In an embodiment, the method includes placing the transfer mold and the device substrate into aligned contact such that the solder pillar is in contact with the wettable pad. In an embodiment, the method includes forming a metallic bond between the solder pillar and the wettable pad. In an embodiment, the method includes removing the mold substrate and first photoresist layer.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric Peter Lewandowski, Jae-Woong Nah, Jeng-Bang Yau, Peter Jerome Sorce
  • Publication number: 20200402984
    Abstract: Semiconductor structures and methods of making the same. The semiconductor structures including at least two vertically stacked nanosheet devices. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (HNS devices) that are stacked vertically, on top of each other, relative to a top surface of a substrate. The plurality of HNS devices including a first HNS device and a second HNS device that each have source and drain structures.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan, Jeng-Bang Yau
  • Publication number: 20200363393
    Abstract: A biosensor includes a bulk silicon substrate and a vertical bipolar junction transistor (BJT) formed on at least a portion of the substrate. The BJT includes an emitter region, a collector region and an epitaxially grown intrinsic base region between the emitter and collector regions. The biosensor further includes a sensing structure formed on at least a portion of two vertical surfaces of the intrinsic base region of the BJT. The sensing structure includes a channel/trench opening, exposing the intrinsic base region on at least first and second opposing sides thereof, and at least one dielectric layer formed in the channel/trench opening and contacting at least a portion of the intrinsic base region, the dielectric layer being configured to respond to charges in biological molecules.
    Type: Application
    Filed: October 7, 2019
    Publication date: November 19, 2020
    Inventors: Alexander Reznicek, Jeng-Bang Yau, Bahman Hekmatshoartabari
  • Patent number: 10839909
    Abstract: A shared floating gate device, the device including an nFET, a pFET including a different material than that of the nFET, and a floating gate.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tak Ning, Jeng-Bang Yau
  • Publication number: 20200343257
    Abstract: The dosimeter has two vertical field effect transistors (VFETs), each VFET with a bottom and top source/drain and channel between them. An implanted charge storage region material lies between and in contact with each of the vertical channels. A trapped charge is within the implanted charge storage region. The amount of the trapped charge is related to an amount of radiation that passes through the implanted charge storage region.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 29, 2020
    Inventors: Jeng-Bang Yau, Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Patent number: 10784347
    Abstract: High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, IC. The presence of the lightly doped upper intrinsic base region increases the total IC and leads to higher current gain, ?, if there is no increase of the base current, IB.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 10777555
    Abstract: A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Publication number: 20200286995
    Abstract: High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, IC. The presence of the lightly doped upper intrinsic base region increases the total IC and leads to higher current gain, ?, if there is no increase of the base current, IB.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: Pouya Hashemi, Tak H. Ning, Jeng-Bang Yau
  • Publication number: 20200273967
    Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, and forming a bottom source/drain region adjacent a base of the fin. In the method, a dielectric layer, a work function metal layer and a first gate metal layer are sequentially deposited on the bottom source/drain region and around the fin. The dielectric layer, the work function metal layer and the first gate metal layer form a gate structure. The method also includes removing the dielectric layer, the work function metal layer and the first gate metal layer from an end portion of the fin, and depositing a second gate metal layer around the end portion of fin in place of the removed dielectric layer, the removed work function metal layer and the removed first gate metal layer. The second gate metal layer contacts the end portion of the fin.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 27, 2020
    Inventors: Alexander Reznicek, Tak H. Ning, Bahman Hekmatshoartabari, Jeng-Bang Yau
  • Patent number: 10741645
    Abstract: A semiconductor device including a base region present within a fin semiconductor structure that is present atop a dielectric substrate. An epitaxial emitter region and epitaxial collector region are present on opposing sides and in direct contact with the fin semiconductor structure. An epitaxial extrinsic base region is present on a surface of the fin semiconductor substrate that is opposite the surface of the fin semiconductor structure that is in contact with the dielectric base.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 10734505
    Abstract: A structure and method of forming a lateral bipolar junction transistor (LBJT) that includes: a first base layer, a second base layer over the first base layer, and an emitter region and collector region present on opposing sides of the first base layer, where the first base layer has a wider-band gap than the second base layer, and where the first base layer includes a III-V semiconductor material.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek, Karthik Balakrishnan, Jeng-Bang Yau