Abstract: A semiconductor radiation monitor (i.e., dosimeter) is provided that has an oxide charge storage region located on a first side of a semiconductor fin and a functional gate structure located on a second side of the semiconductor fin that is opposite the first side. Charges are created in the oxide charge storage region that is located on the first side of the semiconductor fin and detected on the second side of the semiconductor fin by the functional gate structure. Multiple semiconductor fins in parallel can form a dense and very sensitive semiconductor radiation monitor.

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

Abstract: Semiconductor device, memory arrays, and methods of forming a memory cell include or utilize one or more memory cells. The memory cell(s) include a first nanosheet transistor connected to a first terminal, a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal, and an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.

Abstract: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.

Abstract: A semiconductor radiation monitor is provided that includes a charge storage region composed of a dielectric material nanosheet, such as, for example an epitaxial oxide nanosheet, which is sandwiched between a top semiconductor nanosheet and a bottom semiconductor nanosheet. A functional gate structure is located above the top semiconductor nanosheet and beneath the bottom semiconductor nanosheet.

Abstract: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

Abstract: A method for forming an overlap transistor includes forming a gate structure over a III-V material, wet cleaning the III-V material on side regions adjacent to the gate structure and plasma cleaning the III-V material on the side regions adjacent to the gate structure. The III-V material is plasma doped on the side regions adjacent to the gate structure to form plasma doped extension regions that partially extend below the gate structure.

Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.

Abstract: Bipolar junction transistor structures and methods for making the same are provide. The method includes: providing a substrate with an insulator layer and a device layer over the insulator layer, forming an intrinsic base from the device layer, forming emitter and collector regions from the device layer, and after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base.

Abstract: Semiconductor structures and methods of making the same. The semiconductor structures including at least two vertically stacked nanosheet devices. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (HNS devices) that are stacked vertically, on top of each other, relative to a top surface of a substrate. The plurality of HNS devices including a first HNS device and a second HNS device that each have source and drain structures.

Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, and forming a bottom source/drain region adjacent a base of the fin. In the method, a dielectric layer, a work function metal layer and a first gate metal layer are sequentially deposited on the bottom source/drain region and around the fin. The dielectric layer, the work function metal layer and the first gate metal layer form a gate structure. The method also includes removing the dielectric layer, the work function metal layer and the first gate metal layer from an end portion of the fin, and depositing a second gate metal layer around the end portion of the fin in place of the removed dielectric layer, the removed work function metal layer and the removed first gate metal layer. The second gate metal layer contacts the end portion of the fin.

Abstract: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

Abstract: The dosimeter has two vertical field effect transistors (VFETs), each VFET with a bottom and top source/drain and channel between them. An implanted charge storage region material lies between and in contact with each of the vertical channels. A trapped charge is within the implanted charge storage region. The amount of the trapped charge is related to an amount of radiation that passes through the implanted charge storage region.

Abstract: A semiconductor radiation monitor (i.e., dosimeter) is provided that has an oxide charge storage region located on a first side of a semiconductor fin and a functional gate structure located on a second side of the semiconductor fin that is opposite the first side. Charges are created in the oxide charge storage region that is located on the first side of the semiconductor fin and detected on the second side of the semiconductor fin by the functional gate structure. Multiple semiconductor fins in parallel can form a dense and very sensitive semiconductor radiation monitor.

Abstract: A structure and method of forming a lateral bipolar junction transistor (LBJT) that includes: a first base layer, a second base layer over the first base layer, and an emitter region and collector region present on opposing sides of the first base layer, where the first base layer has a wider-band gap than the second base layer, and where the first base layer includes a III-V semiconductor material.

Abstract: A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.

Abstract: An electric static discharge (ESD) diode pair is disclosed. The first diode of the device includes a first diode junction portion having vertically orientated and horizontally oriented portions of a first conductivity and a second diode junction portion of a second conductivity in direct contact with both of the vertically orientated and horizontally orientated portions of the first diode junction portion. The second diode of the device includes a first diode junction portion having vertically orientated and horizontally oriented portions of a second conductivity and a second diode junction portion having a first conductivity in direct contact with both of the vertically orientated and horizontally orientated portions of the first diode junction portion. A common electrical contact is in direct contact first diode junction portion for each of the first diode and the second diode.

Abstract: A semiconductor structure that occupies only one areal device area is provided that includes a charge storage region sandwiched between a pFET nanosheet device and an nFET nanosheet device. The charge storage region is an epitaxial oxide nanosheet that is lattice matched to an underlying first silicon channel material nanosheet and an overlying second silicon channel material nanosheet. The semiconductor structure can be used as an EPROM device.

Abstract: In an embodiment, a method for forming a solder bump includes preparing a transfer mold having a solder pillar extending from a mold substrate and through a first photoresist layer and having a shape partially defined by a second photoresist layer that is removed prior to transfer of the solder. In an embodiment, the mold substrate is flexible. In an embodiment, the transfer mold is flexible. In an embodiment, the method includes providing a device substrate having a wettable pad. In an embodiment, the method includes placing the transfer mold and the device substrate into aligned contact such that the solder pillar is in contact with the wettable pad. In an embodiment, the method includes forming a metallic bond between the solder pillar and the wettable pad. In an embodiment, the method includes removing the mold substrate and first photoresist layer.