Patents by Inventor Jeng Chang

Jeng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210200102
    Abstract: A method for generating an extreme ultraviolet (EUV) radiation includes simultaneously irradiating two or more target droplets with laser light in an EUV radiation source apparatus to produce EUV radiation and collecting and directing the EUV radiation produced from the two or more target droplet by an imaging mirror.
    Type: Application
    Filed: July 27, 2020
    Publication date: July 1, 2021
    Inventors: Chansyun David YANG, Keh-Jeng CHANG, Chan-Lon YANG
  • Publication number: 20210083074
    Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chansyun David YANG, Keh-Jeng CHANG, Chan-Lon YANG
  • Publication number: 20200286781
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu HSIEH, Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU, Ying Ting HSIA
  • Publication number: 20200243378
    Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10679896
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10651079
    Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTUING CO., LTD.
    Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Publication number: 20200043873
    Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.
    Type: Application
    Filed: June 12, 2019
    Publication date: February 6, 2020
    Inventors: Fong-yuan CHANG, Cheng-Hung YEH, Hsiang-Ho CHANG, Po-Hsiang HUANG, Chin-Her CHIEN, Sheng-Hsiung CHEN, Aftab Alam KHAN, Keh-Jeng CHANG, Chin-Chou LIU, Yi-Kan CHENG
  • Publication number: 20190139822
    Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU, Ying Ting HSIA
  • Publication number: 20190088542
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 21, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10174322
    Abstract: Disclosed herein is novel double-stranded short interfering ribonucleic acid (siRNA) capable of suppressing the translation of Aurora-A mRNA. Also disclosed are use of the novel siRNA as disclosed herein for manufacturing a medicament suitable for treating a cancer, which is mediated through epidermal growth factor receptor (EGFR) signaling. Accordingly, a pharmaceutical composition comprising the disclosed novel siRNA molecules is provided; as well as a method of treating a subject suffering from EGFR-mediated cancer via administering to the subject the disclosed novel siRNA molecule.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: January 8, 2019
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Liang-Yi Hung, Chien-Hsien Lai, Ta-Chien Tseng, Jeng-Chang Lee, Bo-Wen Lin
  • Patent number: 10157782
    Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10083863
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Publication number: 20180166332
    Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.
    Type: Application
    Filed: January 24, 2018
    Publication date: June 14, 2018
    Inventors: Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU, Ying Ting HSIA
  • Patent number: 9905456
    Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Publication number: 20180037888
    Abstract: Disclosed herein is novel double-stranded short interfering ribonucleic acid (siRNA) capable of suppressing the translation of Aurora-A mRNA. Also disclosed are use of the novel siRNA as disclosed herein for manufacturing a medicament suitable for treating a cancer, which is mediated through epidermal growth factor receptor (EGFR) signaling. Accordingly, a pharmaceutical composition comprising the disclosed novel siRNA molecules is provided; as well as a method of treating a subject suffering from EGFR-mediated cancer via administering to the subject the disclosed novel siRNA molecule.
    Type: Application
    Filed: February 23, 2016
    Publication date: February 8, 2018
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Liang-Yi HUNG, Chien-Hsien LAI, Ta-Chien TSENG, Jeng-Chang LEE, Bo-Wen LIN
  • Patent number: 9775577
    Abstract: A method for detecting bone structure includes allocating at least one bone portion from a bone image composed by pixels each including luminance value relating to bone structural parameter; aligning a major axis of principal axes of moment of inertia of the bone portion to a principal axis of Cartesian coordinate system; a cortical bone area of the bone portion intersecting at least one principal plane perpendicular to the principal axis, and each principal plane forming an outer and inner contour line of the cortical bone area; processing an analytic algorithm for the bone structural parameter; calculating distributed state of the bone structural parameter in each principal plane to obtain a distributed state of the bone structural parameter of the bone portion; and obtaining a distributed state of the bone structural parameter of the bone portion by assembling distributed state of the bone structural parameter of each bone portion.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: October 3, 2017
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Wei-Jeng Chang, Chia-Yang Sun, Charlie H. Chang, Huang-Wen Huang, Po-Ying Li, Ching-I Hsieh, Cheng-Wei Ku, Kuen-Long Tasi
  • Patent number: 9691809
    Abstract: Disclosed is a method of fabricating an image sensor device, such as a BSI image sensor, and more particularly, a method of forming a dielectric film in a radiation-absorption region without using a conventional plasma etching causing roughness on the surface and non-uniformity within a die and a wafer. The method includes providing layers comprising a substrate having radiation sensors adjacent its front surface, an anti-reflective layer formed over the back surface of the substrate, a sacrificial dielectric layer formed over the anti-reflective layer, and a conductive layer formed over the sacrificial dielectric layer in a radiation-blocking region. The method further includes removing the sacrificial dielectric layer in the radiation-absorption region completely by a highly selective etching process and forming a dielectric film on the anti-reflective layer by deposition such as CVD or PVD while precisely controlling the thickness.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeng Chang Her, Hung Jui Chang, Li Te Hsu, Chung-Bin Tseng
  • Patent number: 9484207
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a wafer having a central portion and a peripheral portion surrounding the central portion. The method includes forming a first dielectric layer over the central portion. The first dielectric layer has first contact openings exposing conductive regions of the wafer. The method includes forming a protective layer over the peripheral portion. The method includes after forming the protective layer, performing a metal silicide process to form metal silicide structures over the conductive regions of the wafer.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: November 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jeng-Chang Her, Chia-Cheng Lin, Hung-Jui Chang, Yu-Sheng Su, Shu-Huei Suen
  • Publication number: 20160302748
    Abstract: The present invention provides a method and system for detection of bone structure, the method executing operation process and image reconstruction according to an image of a skeleton captured by CT scanner, to present distributed state of a bone structural parameter of the skeleton for diagnosing.
    Type: Application
    Filed: November 20, 2015
    Publication date: October 20, 2016
    Applicant: National Applied Research Laboratories
    Inventors: Wei-Jeng CHANG, Chia-Yang SUN, Charlie H. CHANG, Huang-Wen HUANG, Po-Ying LI, Ching-I HSIEH, Cheng-Wei KU, Kuen-Long TASI
  • Publication number: 20150348838
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a wafer having a central portion and a peripheral portion surrounding the central portion. The method includes forming a first dielectric layer over the central portion. The first dielectric layer has first contact openings exposing conductive regions of the wafer. The method includes forming a protective layer over the peripheral portion. The method includes after forming the protective layer, performing a metal silicide process to form metal silicide structures over the conductive regions of the wafer.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 3, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jeng-Chang HER, Chia-Cheng LIN, Hung-Jui CHANG, Yu-Sheng SU, Shu-Huei SUEN