Abstract: An input output circuit and a self-biased circuit are provided. The self-biased circuit includes a tracking circuit, a biasing control circuit and first to fourth transistors. The tracking circuit receives a first power voltage, and generates a bias voltage according to variation of the first power voltage. The biasing control circuit generates a first control signal, a second control signal and a third control signal according to the first power voltage and a voltage on a pad. The first transistor is coupled to the pad and controlled by the first control signal. The second transistor is controlled by the second control signal to provide a bias voltage. The third transistor is coupled to the pad and controlled by the third control signal and generates a fourth control signal according to the voltage on the pad. The fourth transistor is controlled by the fourth control signal to generate the bias voltage.

Abstract: A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.

Abstract: A electrostatic discharge (ESD) protection apparatus for an integrated circuit (IC) is provided. A first electrostatic current rail and a second electrostatic current rail of the ESD protection apparatus do not directly connected to any bonding pad of the IC. The ESD protection apparatus further includes a clamp circuit and four ESD protection circuits. The clamp circuit is coupled between the first electrostatic current rail and the second electrostatic current rail. A first ESD protection circuit is coupled between the first electrostatic current rail and a signal pad of the IC. A second ESD protection circuit is coupled between the signal pad and the second electrostatic current rail. A third ESD protection circuit is coupled between a first power rail and the second electrostatic current rail. A fourth ESD protection circuit is coupled between the second electrostatic current rail and a second power rail.

Abstract: A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.

Abstract: An integrated circuit (IC) including a unit area, a first input/output (IO) cell, a second IO cell, an electrostatic discharge (ESD) component, a first IO pad and a second IO pad is provided. The unit area is divided into several subareas, wherein a subarea of an ith column and a jth row of those subareas is defined as SA(i,j). The first IO cell is arranged in subareas SA(i,j) and SA(i,j+1) of those subareas. The second IO cell is arranged in a subarea SA(i+1,j+1) of those subareas. The ESD component is arranged in at lease one of the subareas of the jth row. The first IO pad is arranged on the first IO cell, and electrically connected to the first IO cell. The second IO pad is arranged on the second IO cell, and electrically connected to the second IO cell.

Abstract: An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving.

Abstract: An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving.

Abstract: A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.

Abstract: A layout architecture having high-performance and high-density design used in a standard cell integrated circuit is provided. The layout architecture includes a substrate, a first conductor, a second conductor, a third conductor, a fourth conductor, a first device region, a second device region, a third device region and a forth device region. The first device region is arranged adjacent to the first conductor on the substrate. The second device region is arranged adjacent to the first device region on the substrate and is arranged beneath the second conductor. The third device region is arranged adjacent to the second device region on the substrate and is arranged beneath the third conductor. The fourth device region is arranged between the third device region and the fourth conductor on the substrate.

Abstract: A data retention device includes a first latch disposed between a data input terminal and a data output terminal for storing a data signal received from the data input terminal and transmitting the data signal through a data forward path to the data output terminal according to a clock signal in an operational mode; a second latch disposed in a branch of the data forward path between the first latch and the data output terminal for receiving the data signal in the operational mode and retaining the data signal in a sleep mode; and a first tri-state buffer disposed in the data forward path between the first latch and the branched second latch and enabled to conduct the data forward path in the operational mode and disabled to cut off the data forward path in the sleep mode according to a data retention signal.

Abstract: A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D.

Abstract: A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.

Abstract: A latch includes a data input terminal for receiving a data signal; a data output terminal for outputting the data signal; a first control terminal for receiving a control signal to set or reset the data signal derived from the data output terminal; a sleep signal input terminal for receiving a sleep signal to determine a sleep mode; a first logic circuit having input terminals coupled to the data input terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data output terminal; and a second logic circuit having input terminals coupled to the data output terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data input terminal; wherein the first logic circuit or the second logic circuit ignores the first control signal in response to the sleep signal when the latch is operated in the sleep mode.

Abstract: The present invention is a scan flip-flop circuit with extra hold time margin. The scan flip-flop circuit includes a multiplexer, a sense amplifier and a latch. The latch includes a generation unit for generating an output signal in response to a first signal and a second signal outputted from the sense amplifier, and a storage unit receives the second signal and the output signal and maintains the output signal of the latch when the first signal and the second signal are non-activated.

Abstract: A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.

Abstract: Electronic cells/cell library and related technology/method capable of achieving high integration of integrated circuits. In one embodiment, the proposed technology adopts cells with cell heights equal to a non-integer multiplication of the routing track to establish a cell library, so a layout area of each cell is reduced. Further, higher integration of integrated circuit can be achieved by applying the proposed cells in integrated circuits.

Abstract: A layout architecture having high-performance and high-density design used in a standard cell integrated circuit is provided. The layout architecture includes a substrate, a first conductor, a second conductor, a third conductor, a fourth conductor, a first device region, a second device region, a third device region and a forth device region. The first device region is arranged adjacent to the first conductor on the substrate. The second device region is arranged adjacent to the first device region on the substrate and is arranged beneath the second conductor. The third device region is arranged adjacent to the second device region on the substrate and is arranged beneath the third conductor. The forth device region is arranged between the third device region and the forth conductor on the substrate.

Abstract: A low power consuming semiconductor device comprises a p substrate, a first semiconductor cell formed over the p substrate, a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell, and a tap cell for coupling a power pin to n-well structures of the first semiconductor cell and the second semiconductor cell, and for coupling a ground pin to the p substrate. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.

Abstract: A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.

Abstract: A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.