Patents by Inventor Jeng-Huang Wu

Jeng-Huang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7046493
    Abstract: An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: May 16, 2006
    Assignee: Faraday Technology Corp.
    Inventors: Sheng-Hua Chen, Hung-Yi Chang, Jeng-Huang Wu
  • Publication number: 20050285689
    Abstract: A CMOS Pierce crystal oscillator. A clock generator with activation control, for generating a clock signal. The clock generator comprises an amplifier, a shaping circuit and a diagnostic circuit. The amplifier is capable of being coupled to an external oscillation source through an input pad and an output pad to generate an oscillating signal, the shaping circuit is capable of being coupled to the output pad, for shaping the oscillating signal to generate a clock signal, and the diagnostic circuit is capable of being coupled to the output pad, for asserting a ready signal when amplitude of the oscillating signal exceeds a predetermined portion of a full swing voltage.
    Type: Application
    Filed: June 24, 2004
    Publication date: December 29, 2005
    Inventors: Jeng-Huang Wu, Sheng-Hua Chen
  • Publication number: 20050128670
    Abstract: An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode.
    Type: Application
    Filed: December 12, 2003
    Publication date: June 16, 2005
    Inventors: Sheng-Hua Chen, Hung-Yi Chang, Jeng-Huang Wu
  • Patent number: 6882188
    Abstract: An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: April 19, 2005
    Assignee: Faraday Technology Corp.
    Inventors: Sheng-Hua Chen, Hung-Yi Chang, Jeng-Huang Wu
  • Publication number: 20050068069
    Abstract: An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Sheng-Hua Chen, Hung-Yi Chang, Jeng-Huang Wu
  • Patent number: 6861874
    Abstract: An input/output buffer. An input/output circuit is composed of a first PMOS transistor and a first NMOS transistor, has an I/O port coupled to an I/O pad, and a N-well region. An N-well control circuit controls the voltage level at the N-well region of the first PMOS transistor according to input signals at the I/O pad. A P-gate control circuit receives a second gate control signal and outputs to the gate of the first PMOS transistor. The P-gate control circuit is composed of a transmission gate and a third PMOS transistor. The transmission gate and the third PMOS transistor do not have to follow the design rule for ESD, and the wafer area required for the P-gate control circuit can be decreased because the P-gate control circuit is not directly connected to the I/O pad.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: March 1, 2005
    Assignee: Faraday Technology Corp.
    Inventors: Sheng-Hua Chen, Hung-Yi Chang, Jeng-Huang Wu
  • Patent number: 6741130
    Abstract: A high-speed output transconductance amplifier (OTA) capable of operating at different voltage levels. The high-speed output transconductance amplifier configures a cross-coupled circuit with programmable switches to offer a high-speed receiver capable of operating at lower voltage and normal voltage, for example, a receiver can be operated in both for SSTL-3 (3.3V system) and SSTL-2 (2.5V system).
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: May 25, 2004
    Inventors: Meng-Jer Wey, Jeng-Huang Wu
  • Publication number: 20040056716
    Abstract: A high-speed output transconductance amplifier (OTA) capable of operating at different voltage levels. The high-speed output transconductance amplifier configures a cross-coupled circuit with programmable switches to offer a high-speed receiver capable of operating at lower voltage and normal voltage, for example, a receiver can be operated in both for SSTL-3 (3.3V system) and SSTL-2 (2.5V system).
    Type: Application
    Filed: September 23, 2002
    Publication date: March 25, 2004
    Inventors: Meng-Jer Wey, Jeng-Huang Wu
  • Patent number: 6456115
    Abstract: A clock gate buffering circuit is having a functional circuit without a latch that receives a clock and an enable signal. A logic voltage of an enable signal sends a corresponding clock gate signal to provide the other circuit when the clock of the functional circuit is in a rising edge. Also, the logical voltage of the enable signal sends a corresponding clock gate signal to provide the other circuit when this functional circuit is also in falling edge.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: September 24, 2002
    Assignee: Faraday Technology Corp.
    Inventors: Guo-Wei Li, Jeng-Huang Wu, Chih-Fu Chien
  • Publication number: 20020084825
    Abstract: The small swing output buffer of the present invention comprises, for example, four transistors or FETs; P1, P2, N1, and N2. The source of P2 is connected to Vcc and the drain of P2 is connected to the source of P1. The drain of PI is connected to the source of N1. The drain of N1 is connected to the source of N2. The drain of N2 is connected to ground. The input signal to the output buffer is fed into input IN which is connected to the gates of P1 and N1. The output of the output buffer is output OUT which is connected to the drain of P1 and the source of N1. For the small swing output buffer, when the input signal is at a high potential, P1 and P2 are turned off and N1 and N2 are turned on which pulls down the potential of OUT towards ground potential. Since FETs have a threshold voltage, the potential of the output OUT cannot be completely pulled to ground potential. Therefore, the potential of the output OUT when the input signal applied to IN is a high potential, is the threshold voltage (Vt) of N2.
    Type: Application
    Filed: January 4, 2001
    Publication date: July 4, 2002
    Inventors: Yi-Ren Hwang, Jeng-Huang Wu
  • Publication number: 20010013796
    Abstract: A clock gate buffering circuit is having a functional circuit without a latch that receives a clock and an enable signal. A logic voltage of an enable signal sends a corresponding clock gate signal to provide the other circuit when the clock of the functional circuit is in a rising edge. Also, the logical voltage of the enable signal sends a corresponding clock gate signal to provide the other circuit when this functional circuit is also in falling edge.
    Type: Application
    Filed: February 8, 2001
    Publication date: August 16, 2001
    Inventors: Guo-Wei Li, Jeng-Huang Wu, Chih-Fu Chien
  • Patent number: 6160457
    Abstract: A universal crystal-oscillator input/output (I/O) circuit is provided for use with an ASIC (Application Specific Integrated Circuit) device, and which can help enhance the electrostatic discharge (ESD) protection on the ASIC device in Charge Device Mode (CDM). This universal crystal-oscillator I/O circuit can help reduce the total number of I/O components in the ASIC library used to construct the IC device, allowing the design and management of ASIC library to be more simplified and convenient, making ASIC more cost-effective to implement. Moreover, this universal crystal-oscillator I/O circuit can help improve the performance of the oscillator circuit, allowing ASIC designers to have more convenience and flexibility in ASIC design. It can be fast in starting oscillation and low in power consumption.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: December 12, 2000
    Assignee: Faraday Technology Corp.
    Inventor: Jeng-Huang Wu
  • Patent number: 5974476
    Abstract: An input/output (I/O) device with programmable I/O characteristics is provided for use on an integrated circuit to serve as a communication interface whose input/output characteristics can be set through programmable means to be matched to the external circuitry to which the IC chip is connected for use. This allows the IC chip on which the I/O device is provided to be matched for use with various kinds of external systems. Further, the I/O device can also be provided with a self-control feature that can detect whether the I/O characteristics of the I/O device are matched to the external circuitry and, if not, automatically set the I/O device to the required I/O characteristic. The I/O device can prevent an IC chip from being discarded due to a mismatch in the I/O characteristics with the external circuitry to which the IC chip is connected for use.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: October 26, 1999
    Assignee: Faraday Technology Corp.
    Inventors: Tin-Hao Lin, Jeng-Huang Wu