Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.

Abstract: The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.

Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.

Abstract: This invention discloses a semiconductor device and a method for fabricating the same. The method includes providing a flexible carrier board having a first surface and a second surface opposite thereto; forming a metal lead layer and a first heat dissipating metal layer on the first surface of the flexible carrier board, and forming a second heat dissipating metal layer on the second surface of the flexible carrier board; providing a chip having an active surface and an opposed non-active surface, wherein a plurality of solder pads are formed on the active surface of the chip, each of the solder pads has a metal bump formed thereon and corresponding in position to the metal lead layer, and heat dissipating bumps are formed between the metal bumps corresponding in position to the first heat dissipating metal layer.

Abstract: A semiconductor package and a method for fabricating the same are disclosed, which includes: providing a carrier board, forming a plurality of metal bumps on the carrier board, forming a metal layer on the carrier board to encapsulate the metal bumps, having at least one semiconductor chip electrically connected to the metal layer, then forming an encapsulant on the carrier board to encapsulate the semiconductor chip, and next removing the carrier board and the metal bumps to correspondingly form a plurality of grooves on surface of the encapsulant, wherein bottom and sides of the grooves are covered with the metal layer to allow electroconductive components to be effectively positioned in the grooves and completely bonded with the metal layer.

Abstract: A semiconductor package substrate includes a body having an upper surface and a lower surface opposite to one another, a plurality of circuit layers formed in the body, a plurality of solder pads formed on the upper surface of the body, and a plurality of solder ball pads formed on the lower surface of the body. Each of the solder pads is electrically connected to one of the solder ball pads via the circuit layers and conductive structures disposed between the circuit layers, wherein the circuit layers and conductive structures are configured to expand outwardly in a fan-out manner so as to provide more space between the circuit layers closer to the lower surface of the body such that part of the solder pad-solder ball pad electrical connections can comprise a plurality of parallel connected conductive structures formed in the space, thereby enhancing the heat conducting passageway and the effect of heat-dissipation without having to dispose more solder pads on surface of the substrate.

Abstract: A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process.

Abstract: A semiconductor package and a fabrication method thereof are proposed. A lead frame is provided between a chip and a substrate in a window ball grid array semiconductor package, wherein an active surface of the chip is electrically connected to the lead frame via bonding wires formed in an opening of the substrate and is electrically connected to the substrate via the lead frame. The provision of lead frame can improve the heat dissipating efficiency and electrical performances. The bonding wires located in the opening of the substrate eliminate the prior-art drawback of requiring different molds in response to different opening structures of a substrate.

Abstract: A system for testing a die (or chip) of a semiconductor wafer is disclosed. It features measuring the temperature of the die according to a light beam originating from the die. The temperature so measured functions as part of test record and/or the basis for controlling the temperature of the die. Measuring the temperature of a die in such a way will replace measuring the temperature of a die conventionally via the wafer carrier on which the die being tested is placed. The system comprises: a die test device for testing the performance and/or quality of a die; and a temperature detector separated from the die and the wafer, for measuring the temperature of the die according to a light beam originating from the die. The temperature detector may be either connected to or embedded in the die test device, or be placed at another location. Another feature is the use of a light emitter which produces light beams directed to the die or the wafer for providing heat thereto.

Abstract: The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.

Abstract: A semiconductor device, a chip structure thereof, and a method for fabricating the same are proposed. The method involves cutting a wafer with an array of chips twice so as to separate the chips and to form a chip structure. The first cutting is wider than the second cutting, and both are performed on an inactive surface of each of the chips. The chip structure includes a protruding portion formed on the inactive surface. The chip structure is electrically connected to a substrate by conductive bumps in a flip-chip manner and mounted with a heat sink. A decrease in contact area between the chip and the heat sink reduces warpage caused to the semiconductor device by thermal stress, thus preventing delamination of the heat sink and cracking of the conductive bumps, and reducing the expense and time spent on finding suitable underfill materials.

Abstract: A semiconductor package and a fabrication method thereof are proposed. A lead frame is provided between a chip and a substrate in a window ball grid array semiconductor package, wherein an active surface of the chip is electrically connected to the lead frame via bonding wires formed in an opening of the substrate and is electrically connected to the substrate via the lead frame. The provision of lead frame can improve the heat dissipating efficiency and electrical performances. The bonding wires located in the opening of the substrate eliminate the prior-art drawback of requiring different molds in response to different opening structures of a substrate.

Abstract: A semiconductor package and a fabrication method thereof are proposed. A lead frame is provided between a chip and a substrate in a window ball grid array semiconductor package, wherein an active surface of the chip is electrically connected to the lead frame via bonding wires formed in an opening of the substrate and is electrically connected to the substrate via the lead frame. The provision of lead frame can improve the heat dissipating efficiency and electrical performances. The bonding wires located in the opening of the substrate eliminate the prior-art drawback of requiring different molds in response to different opening structures of a substrate.

Abstract: A semiconductor package and a fabrication method thereof are proposed. A lead frame is provided between a chip and a substrate in a window ball grid array semiconductor package, wherein an active surface of the chip is electrically connected to the lead frame via bonding wires formed in an opening of the substrate and is electrically connected to the substrate via the lead frame. The provision of lead frame can improve the heat dissipating efficiency and electrical performances. The bonding wires located in the opening of the substrate eliminate the prior-art drawback of requiring different molds in response to different opening structures of a substrate.

Abstract: A lead frame and a semiconductor package with the lead frame are provided. The lead frame includes a die pad for mounting at least one semiconductor chip thereon; at least one grounding portion protruded from the die pad; and a plurality of leads. The grounding portion has a grounding surface and an opposing bottom surface, wherein the thickness of the grounding portion is smaller than that of the die pad, and a ground pad is formed on the grounding surface for connecting at least one grounding wire to the chip for transmitting ground signals. A plurality of bonding wires are connected from the chip to the leads such that the chip can be electrically connected to an external device via the bonding wires and leads. By the above arrangement, the grounding wire can be prevented from breakage by thermal stress in a high-temperature process, and the production yield is improved.

Abstract: A lead frame and a semiconductor package with the lead frame are provided. The lead frame includes a die pad for mounting at least one semiconductor chip thereon; at least one grounding portion protruded from the die pad; and a plurality of leads. The grounding portion has a grounding surface and an opposing bottom surface, wherein the thickness of the grounding portion is smaller than that of the die pad, and a ground pad is formed on the grounding surface for connecting at least one grounding wire to the chip for transmitting ground signals. A plurality of bonding wires are connected from the chip to the leads such that the chip can be electrically connected to an external device via the bonding wires and leads. By the above arrangement, the grounding wire can be prevented from breakage by thermal stress in a high-temperature process, and the production yield is improved.

Abstract: A cavity-down ball grid array package includes a substrate having a through cavity provided therein. A heat sink is attached to the substrate and a semiconductor chip in the cavity is attached to the heat sink and electrically connected to the substrate. A ball grid array is on the substrate and on the semiconductor chip.

Abstract: A cavity-down ball grid array package includes a substrate having a through cavity provided therein. A heat sink is attached to the substrate and a semiconductor chip in the cavity is attached to the heat sink and electrically connected to the substrate. A ball grid array is on the substrate and on the semiconductor chip.

Abstract: A multi-chip semiconductor package with a heat dissipating structure is proposed, in which a chip receiving cavity and an opening respectively formed in the heat dissipating structure and a chip carrier, are used to accommodate semiconductor chips therein with the chips being in direct contact with the heat dissipating structure, allowing heat generated by the chips to be rapidly dissipated through the heat dissipating structure. With the provision of through holes for interconnecting the chip receiving cavity and opening, gold wires pass the through holes and electrically connect the chips to the chip carrier. Such a structure with chips embedded in the chip receiving cavity and opening makes internal elements to be more compactly arranged in the semiconductor package, which is preferable in response to profile miniaturization of electronic product development.

Abstract: An externally-embedded heat-dissipating device is designed for use with a BGA (Ball Grid Array) IC package for dissipating the IC-produced heat during operation to the atmosphere. that can help further increase the efficiency of heat dissipation from the BGA IC package. The heat-dissipating device is characterized in that it can be externally embedded in the top surface of the encapsulant without having to be supported on the substrate, and also in that it can help reduce the heat path from the IC chip to the heat-dissipating device so that heat-dissipation efficiency can be further increased as compared to the prior art. Further, the heat-dissipating device can help reduce manufacture cycle time and cost and also help prevent delamination, flash, and popcorn effect that would otherwise occur in the case of the prior art. It also can help save layout space over the substrate for compact design of the package.