Patents by Inventor Jenn-Yu Lin

Jenn-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8710813
    Abstract: A low drop-out regulator is disclosed. An unregulated DC input terminal receives an input voltage. A pass circuit is coupled between the unregulated DC input terminal and a regulated DC output terminal for supplying a power to the regulated DC output terminal. An amplifying circuit controls the pass circuit for providing a constant voltage or/and a constant current in response to an output voltage or/and an output current.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: April 29, 2014
    Assignee: System General Corp.
    Inventors: Ta-Yung Yang, Jenn-Yu Lin
  • Patent number: 7923787
    Abstract: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: April 12, 2011
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu Lin, Ta-Yung Yang
  • Patent number: 7847365
    Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: December 7, 2010
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu Lin, Ta-yung Yang
  • Publication number: 20090256540
    Abstract: A low drop-out regulator according to the present invention comprises an unregulated DC input terminal receiving an input voltage. A pass circuit is coupled between the unregulated DC input terminal and a regulated DC output terminal for supplying a power to the regulated DC output terminal. An amplifying circuit controls the pass circuit for providing a constant voltage or/and a constant current in response to an output voltage or/and an output current.
    Type: Application
    Filed: April 8, 2009
    Publication date: October 15, 2009
    Inventors: Ta-Yung Yang, Jenn-Yu Lin
  • Publication number: 20090050962
    Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.
    Type: Application
    Filed: October 14, 2005
    Publication date: February 26, 2009
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu Lin, Ta-yung Yang
  • Publication number: 20080290410
    Abstract: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.
    Type: Application
    Filed: October 14, 2005
    Publication date: November 27, 2008
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu Lin, Ta-yung Yang
  • Publication number: 20070178648
    Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
    Type: Application
    Filed: March 6, 2007
    Publication date: August 2, 2007
    Applicant: SYSTEM GENERAL CORP.
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu Lin, Tuo-Hsin Chien
  • Publication number: 20070117328
    Abstract: A structure of a vertical transistor with field region is provided. The vertical transistor comprises a field-doping region formed in a substrate next to a core region of the vertical transistor By modulating the doping density, length, and geometrical pattern of the field region, and by connecting the field region to respective well of rim core regions of the vertical transistor, the present invention realizes a stable breakdown voltage with short length of the field region. Therefore, the device area and the manufacturing cost can be reduced.
    Type: Application
    Filed: January 11, 2007
    Publication date: May 24, 2007
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-yu Lin, Ta-yung Yang
  • Publication number: 20070052030
    Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 8, 2007
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu Lin, Tuo-Hsin Chien
  • Publication number: 20070052032
    Abstract: An electrostatic discharge (ESD) device with latch-up immunity is provided. The ESD device has an equivalent SCR structure when a supply voltage is not applied thereto and has an equivalent PN diode structure when the supply voltage is applied thereto, thus freeing the ESD device from the latch-up phenomenon.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 8, 2007
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu Lin, Tuo-Hsin Chien
  • Publication number: 20070004150
    Abstract: An electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided. The semiconductor structure has multi-stage protection semiconductor circuit finction and adjustable discharge capacity. The single-trigger or multi-trigger semiconductor structure may be fabricated by using the conventional semiconductor process, and can be applied to IC semiconductor design and to effectively protect the important semiconductor devices and to prevent the semiconductor devices from ESD damage. In particular, the present invention can meet the requirements of high power semiconductor device and has better protection function compared to conventional ESD protection circuit. In the present invention, a plurality of N-wells or P-wells connected in parallel are used to adjust the discharge capacity of various wells in the P-substrate so as to improve the ESD protection capability and meet different power standards.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 4, 2007
    Applicant: SYSTEM GENERAL CORP.
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-yu Lin, Ta-yung Yang
  • Publication number: 20070001229
    Abstract: An electrostatic discharge (ESD) device has a parasitic SCR structure and a controllable trigger voltage. The controllable trigger voltage of the ESD device is achieved by modulating a distance between an edge of a lightly doped well and an edge of a heavily doped region located at two ends of the lightly doped well. Since the distance and the trigger voltage are linearly proportional, the trigger voltage can be set to a specific value from a minimum value to a maximum value.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 4, 2007
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu Lin, Tuo-Hsin Chien
  • Publication number: 20060220170
    Abstract: A high-voltage MOSFET having isolation structure is provided. An N-type MOSFET includes a first deep N-type well. A first P-type region is formed in the first deep N-type well to enclose a first source region and a first contact region. A first drain region is formed in the first deep N-type well. A P-type MOSFET includes a second deep N-type well. A second P-type region is formed in the second deep N-type well to enclose a second drain region. A second source region and a second contact region are formed in the second deep N-type well. A polysilicon gate oxidation layer is disposed above the thin gate oxidation layer and the thick field oxidation layer to control the current in the channel of the MOSFET. Separated P-type regions provide further isolation between MOSFETs. A first gap and a second gap increase the breakdown voltage of the high-voltage MOSFET.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-yu Lin, Ta-yung Yang
  • Publication number: 20060197153
    Abstract: A structure of a vertical transistor with field region is provided. The vertical transistor comprises a field-doping region formed in a substrate next to a core region of the vertical transistor. By modulating the doping density, length, and geometrical pattern of the field region, and by connecting the field region to respective well of rim core regions of the vertical transistor, the present invention realizes a stable breakdown voltage with short length of the field region. Therefore, the device area and the manufacturing cost can be reduced.
    Type: Application
    Filed: February 23, 2005
    Publication date: September 7, 2006
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-yu Lin, Ta-yung Yang
  • Publication number: 20060133118
    Abstract: A multiple-sampling circuit is proposed for measuring a voltage signal and a discharge time of a transformer. Sampling signals are used for generating hold voltages by alternately sampling the reflected voltage from the transformer. A buffer amplifier generates a buffer voltage from the higher voltage of hold voltages. A sampling switch periodically conducts the buffer voltage to produce a voltage-feedback signal. The voltage-feedback signal is proportional to an output voltage of the switching circuit. A threshold signal added to the reflected voltage signal produces a level-shift reflected signal. A discharge-time signal is generated as the switching signal is disabled. The discharge-time signal is disabled once the level-shift signal is lower than the voltage-feedback signal. The pulse width of the discharge-time signal is therefore correlated to the discharge time of the transformer. The sampling signals are enabled to generate hold voltages only when the discharge-time signal is enabled.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 22, 2006
    Inventors: Ta-yung Yang, Guo-Kiang Hung, Jenn-yu Lin
  • Publication number: 20060056204
    Abstract: The present invention discloses a switching control circuit for a primary-side controlled power converter. A voltage-waveform detector produces a voltage-feedback signal and a discharge-time signal. A current-waveform detector generates a current-waveform signal by measuring a primary-side switching current. An integrator generates a current-feedback signal by integrating the current-waveform signal with the discharge time. A time constant of the integrator is correlated with the switching frequency, thus the current-feedback signal is proportional to an output current of the power converter. A PWM circuit controls the pulse width of the switching signal in response to the outputs of a voltage-loop error amplifier and a current-loop error amplifier. The output voltage and the maximum output current of the power converter are therefore regulated.
    Type: Application
    Filed: September 16, 2004
    Publication date: March 16, 2006
    Inventors: Ta-yung Yang, Guo-Kiang Hung, Jenn-yu Lin, Chuh-Ching Li, Shao-Wei Chiu
  • Publication number: 20060055433
    Abstract: A voltage-waveform detector produces a voltage-feedback signal and a discharge-time signal by multi-sampling a voltage signal of a transformer. The discharge-time signal represents a discharge time of a secondary-side switching current. A voltage-loop error amplifier amplifies the voltage-feedback signal and generates a control signal. An off-time modulator correspondingly generates a discharge-current signal and a standby signal in response to the control signal and an under-voltage signal. The under-voltage signal indicates a low supply voltage of the controller. An oscillator produces a pulse signal in response to the discharge-current signal. The pulse signal determines the off-time of the switching signal. A PWM circuit generates the switching signal in response to the pulse signal and the standby signal. The standby signal further controls the off-time of the switching signal and maintains a minimum switching frequency. The switching signal is used for regulating the output of the power supply.
    Type: Application
    Filed: September 16, 2004
    Publication date: March 16, 2006
    Inventors: Ta-yung Yang, Guo-Kiang Hung, Jenn-yu Lin, Chuh-Ching Li, Feng Tsao
  • Publication number: 20060050539
    Abstract: The invention presents a switching control circuit for a primary-side-controlled power converter. A pattern generator produces a digital pattern to control a programmable capacitor that is connected to an oscillator, which produces frequency hopping to reduce the EMI. A voltage-waveform detector produces a voltage-feedback signal and a discharge-time signal by multi-sampling a voltage signal of a transformer. A current-waveform detector and an integrator generate a feedback signal. The integration of a current-waveform signal with a timing signal generates the average-current signal. Time constant of the integrator is correlated to the switching frequency. The oscillator generates the timing signal and a pulse signal in response to the output of a current-loop error amplifier. A PWM circuit generates the switching signal in response to the pulse signal and the output of a voltage-loop error amplifier for switching the switching device and regulating the output of the power converter.
    Type: Application
    Filed: September 9, 2004
    Publication date: March 9, 2006
    Inventors: Ta-yung Yang, Guo-Kiang Hung, Jenn-yu Lin, Feng Tsao, Chiu Wei
  • Publication number: 20060034102
    Abstract: A close-loop PWM controller for a primary-side controlled power converter is provided. A voltage-waveform detector produces a voltage-feedback signal and a discharge-time signal. A current-waveform detector generates a current-waveform signal by measuring a primary-side switching current. An integrator generates a current-feedback signal by integrating the current-waveform signal with the discharge-time signal. A time constant of the integrator is correlated with a switching period of the switching signal, therefore the current-feedback signal is proportional to the output current of the power converter. The close-loop PWM controller further comprises a voltage-loop error amplifier and a current-loop error amplifier. A PWM circuit and comparators control the pulse width of the switching signal in response to the outputs of the voltage-loop error amplifier and the current-loop error amplifier. The output voltage and the maximum output current of the power converter are therefore regulated.
    Type: Application
    Filed: August 12, 2004
    Publication date: February 16, 2006
    Inventors: Ta-yung Yang, Guo-Kiang Hung, Jenn-yu Lin
  • Publication number: 20060033156
    Abstract: A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The source region and P-field blocks enclose the drain region, which makes the LDMOS transistor self-isolated.
    Type: Application
    Filed: August 16, 2004
    Publication date: February 16, 2006
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu Lin, Tuo-Hsin Chien