Patents by Inventor Jenn-Yu Lin

Jenn-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060033156
    Abstract: A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The source region and P-field blocks enclose the drain region, which makes the LDMOS transistor self-isolated.
    Type: Application
    Filed: August 16, 2004
    Publication date: February 16, 2006
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu Lin, Tuo-Hsin Chien
  • Publication number: 20060030107
    Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
    Type: Application
    Filed: August 9, 2004
    Publication date: February 9, 2006
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu Lin, Tuo-Hsin Chien
  • Publication number: 20050285587
    Abstract: An apparatus and method thereof for measuring an output current from a primary side of a power converter are provided. A peak detector is designed to sample a peak value of a converted voltage of a primary-side switching current. A zero-current detector detects a discharge-time of a secondary-side switching current through an auxiliary winding of a transformer. An oscillator generates a switching signal for switching the power converter. An integrator generates an integrated signal by integrating the converted voltage of the primary-side switching peak current with the discharge-time. The time constant of the integrator is correlated with the switching period of the switching signal. The integrated signal is thus proportional to the output current of the power converter.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Inventors: Ta-yung Yang, Guo-Kiang Hung, Jenn-yu Lin
  • Publication number: 20050242796
    Abstract: A method and apparatus to dynamically modify internal compensation of a low dropout (LDO) voltage regulator is provided. The LDO voltage regulator includes an output pass transistor, an error amplifier, a bias transistor and a compensation network. The compensation network is connected between a gate and a drain of the output pass transistor to compensate for the feedback loop. The compensation network and the bias transistor generate pole-zero pairs to perform a maximum 45 degrees phase shift before reaching the crossover frequency in the LDO voltage regulator. Therefore a minimum 45 degrees phase margin is provided for the feedback loop in various load conditions. Furthermore, the pole-zero pairs produced in the LDO voltage regulator are adaptively adjusted according to load conditions, so that the bandwidth is optimized and faster transient response is achieved.
    Type: Application
    Filed: May 3, 2004
    Publication date: November 3, 2005
    Inventors: Ta-yung Yang, Jenn-yu Lin, Chien-Liang Chen
  • Publication number: 20050184338
    Abstract: A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before breakdown occurs. Therefore, a higher breakdown voltage is achieved and a higher doping density of the N-well is allowed. Higher doping density can effectively reduce the on-resistance of the LDMOS transistor. Furthermore, the N-well generated beneath a source diffusion region provides a low-impedance path for a source region, which restrict the transistor current flow in between a drain region and a source region.
    Type: Application
    Filed: February 24, 2004
    Publication date: August 25, 2005
    Inventors: Chih-Feng Huang, Ta-Yung Yang, Jenn-Yu Lin, Tuo-Hsin Chien
  • Publication number: 20050146903
    Abstract: The present invention demonstrates a power-mode controlled power converter for supplying a constant output voltage and a constant output current. A PWM controller of the power-mode controlled power converter generates a PWM signal in response to the voltage sampled from a transformer auxiliary winding. A programmable current-sink and a detection resistor compensate for the voltage drop of an output rectifier. A low-pass filter integrates a switching-current voltage to an average-current signal. An attenuator produces an input-voltage signal from a line-voltage input signal. The PWM controller multiplies the average-current signal with the input-voltage signal to generate a power-control signal. An error-amplifier compares the power-control signal with a power-reference voltage to generate a limit voltage. The limit voltage controls the power delivered from a primary-side circuit to a secondary-side circuit of the power-mode controlled power converter.
    Type: Application
    Filed: January 5, 2004
    Publication date: July 7, 2005
    Inventors: Ta-Yung Yang, Chern-Lin Chen, Jenn-Yu Lin, Guo-Kiang Hung
  • Publication number: 20050024897
    Abstract: The present invention provides a forward power converter with a synchronized rectifying controller. The synchronized rectifying controller has a detection input for detecting the voltage of a secondary winding of a transformer, and thereby accurately measuring the PWM signal. Based on this measurement, the synchronized rectifying controller generates control signals for two secondary-side rectifying MOSFETs. The present invention also introduces a delay time using a timing resistor coupled to the synchronized rectifying controller. This avoids cross-conduction from secondary-side MOSFETs. The present invention also includes an output current-sense mechanism to avoid reverse inductor currents under light-load conditions.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 3, 2005
    Inventors: Ta-Yung Yang, Jenn-Yu Lin, Chern-Lin Chen
  • Publication number: 20050024898
    Abstract: The present invention provides a primary-side flyback power converter that supplies a constant voltage output and a constant current output. To generate a well-regulated output voltage under varying load conditions, a PWM controller is included in the power converter in order to generate a PWM signal controlling a switching transistor in response to a flyback voltage sampled from a first primary winding of the power supply transformer. Several improvements are included in this present invention to overcome the disadvantages of prior-art flyback power converters. Firstly, the flyback energy of the first primary winding is used as a DC power source for the PWM controller in order to reduce power consumption. A double sample amplifier samples the flyback voltage just before the transformer current drops to zero. Moreover, an offset current is pulled from a detection input of the double sample amplifier in order to generate a more accurate DC output voltage.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 3, 2005
    Inventors: Ta-Yung Yang, Jenn-Yu Lin, Chern-Lin Chen
  • Publication number: 20050007083
    Abstract: A regulated power supply having power factor correction control includes a multi-vector error amplifier. The multi-vector error amplifier provides an error signal that is used to regulate a switching mechanism of the power supply. The multi-vector error amplifier acts to provide a low distortion error signal during steady-state operation, while responding rapidly and smoothly to sudden load changes.
    Type: Application
    Filed: July 10, 2003
    Publication date: January 13, 2005
    Inventors: Ta-yung Yang, Yi-Hsin Leu, Chern-Lin Chen, Jenn-Yu Lin
  • Publication number: 20050007088
    Abstract: A PFC-PWM controller with a power saving means is disclosed. A built-in current synthesizer generates a bias current in response to feedback voltages sampled from the PWM circuit and the PFC circuit. The bias current modulates the oscillation frequency to further reduce the switching frequencies of the PWM signal and the PFC signal under light-load and zero-load conditions. Thus, power consumption is greatly reduced. The PFC and the PWM switching signals interleave each other, so that power can be transferred more smoothly from the PFC circuit to the PWM circuit. The saturation of the switching components can be avoided by limiting the maximum on-time of the PWM signal. Further, an external resistor is used to start up the PFC-PWM controller and to provide an AC template signal for PFC control.
    Type: Application
    Filed: July 10, 2003
    Publication date: January 13, 2005
    Inventors: Ta-Yung Yang, Jenn-Yu Lin, Chern-Lin Chen