Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).

Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).

Abstract: A single-step immunoassay method, kit, and reagents for detecting and quantifying contaminant host cell proteins in a recombinant protein sample are described. The method includes the step of adding to immobilized medium comprising a capture reagent including anti-host cell protein antibodies, both the recombinant protein sample and a detection reagent comprising anti-host cell protein antibodies and a detectable moeity. The recombinant protein sample and two reagents are added simultaneously. This single-step format provides greater interaction between the capture antibody, the contaminant host cell proteins that may be present in the recombinant protein sample, and the detection antibody. By providing the opportunity for both antibodies and HCPs to interact at the same time, the one step format allows the formation of the “capture antibody-HCP-detection antibody” complex with all possible HCPs present.

Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).

Abstract: A handle for a safety razor has an elongated cavity within the handle and a body disposed within the elongated cavity and moveable along the cavity under the influence of gravity between two positions. In a first position the razor has a first center of balance. In the second position the razor has a second center of balance different from the first center of balance. The handle has a damping fluid within the cavity or a resilient member to damp the movement of the body.

Abstract: Accordingly, this invention relates to an dry etching process for semiconductor wafers. More particularly, the present invention discloses a dry etching process including a halogen etchant (24) and a nitrogen gas (28) that selectively etches a compound semiconductor material (18) faster than the front-side metal layers (16A)(16B). Further, the dry etching process produces a vertical wall profile on compound semiconductor material (18) in both X (38) and Y (40) crystalline directions without undercutting the top of a via-opening.

Abstract: A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.

Abstract: A method of dry plasma etching a semiconductor structure (20), having at least one semiconductor material layer (21), on a semiconductor wafer (200), involving a dry plasma reaction gas mixture (30i) being chemically selected for, and having an etch rate corresponding to, each semiconductor material layer (21); dividing the semiconductor structure (20) into a masked portion (23a) and an unmasked portion (23b); and sequentially exposing the unmasked portion (23b) of the semiconductor structure (20) to the dry plasma reaction gas mixture (30i).

Abstract: Accordingly, this invention relates to an dry etching process for semiconductor wafers. More particularly, the present invention discloses a dry etching process including a halogen etchant (24) and a nitrogen gas (28) that selectively etches a compound semiconductor material (18) faster than the front-side metal layers (16A)(16B). Further, the dry etching process produces a vertical wall profile on compound semiconductor material (18) in both X (38) and Y (40) crystalline directions without undercutting the top of a via-opening.

Abstract: An improved etching process for creating dimensionally accurate sub-micron and micron via-openings is disclosed. Specifically, this invention discloses a via etching process for a polymer layer (24) deposited on a semiconductor substrate (28) comprising the steps of: placing the semiconductor substrate comprising a polymer layer (24) deposited on the semiconductor substrate, a hard-mask (30) deposited on the polymer layer (24) and a photoresist mask (32) deposited on the hard-mask (30). The invention further, discloses performing a hard-mask opening step (34) comprising releasing a first fluoride gas (36) into the chamber. Furthermore, performing a polymer etching step (40) comprising releasing a second fluoride gas (42) into the chamber is disclosed. The invention also includes a hard-mask removal and tapered via step (46) to increase process margin.

Abstract: A method of dry plasma etching a semiconductor structure (20), having at least one semiconductor material layer (21), on a semiconductor wafer (200), involving a dry plasma reaction gas mixture (30i) being chemically selected for, and having an etch rate corresponding to, each semiconductor material layer (21); dividing the semiconductor structure (20) into a masked portion (23a) and an unmasked portion (23b); and sequentially exposing the unmasked portion (23b) of the semiconductor structure (20) to the dry plasma reaction gas mixture (30i).

Abstract: Embodiments of the invention provide a status register for each channel of a DMA controller. The status register may be used to monitor and record events that occur during DMA data transfers, including timeouts and aborts.

Abstract: Embodiments of the invention provide a status register for each channel of a DMA controller. The status register may be used to monitor and record events that occur during DMA data transfers, including timeouts and aborts.