Patents by Inventor Jens Lupke
Jens Lupke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7117403Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.Type: GrantFiled: July 18, 2001Date of Patent: October 3, 2006Assignee: Infineon Technologies AGInventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lüpke, Jochen Müller, Peter Pöchmüller, Michael Schittenhelm
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Patent number: 7117404Abstract: Test circuit for testing a synchronous memory circuit having a frequency multiplication circuit which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor a test data generator which produces test data on the basis of data control signals received from the external test unit and outputs them to a data output driver a first signal delay circuit for delaying the test data which are output by the test data generator by an adjustable first delay time, a second signal delay circuit for delaying data which are read out of the synchronous memory circuit and are received by a data input driver in the test circuit by an adjustable second delay time, and having a data comparison circuit which compares the test data produced by the test data generator with the data read out of the memory circuit and, on the basis of the comparison result, outputs an indicator signal to the external test unit which indicates whether the synchronouType: GrantFiled: March 26, 2002Date of Patent: October 3, 2006Assignee: Infineon Technologies AGInventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lüpke, Peter Poechmüller, Jochen Mueller, Michael Schittenhelm
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Patent number: 7062690Abstract: A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.Type: GrantFiled: July 18, 2001Date of Patent: June 13, 2006Assignee: Infineon Technologies AGInventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lüpke, Jochen Müller, Peter Pöchmüller, Michael Schittenhelm
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Patent number: 6871306Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.Type: GrantFiled: July 18, 2001Date of Patent: March 22, 2005Assignee: Infineon Technologies AGInventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lüpke, Jochen Müller, Peter Pöchmüller, Michael Schittenhelm
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Patent number: 6862702Abstract: The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.Type: GrantFiled: July 18, 2001Date of Patent: March 1, 2005Assignee: Infineon Technologies AGInventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lüpke, Jochen Müller, Peter Pöchmüller, Michael Schittenhelm
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Patent number: 6839397Abstract: A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.Type: GrantFiled: July 18, 2001Date of Patent: January 4, 2005Assignee: Infineon Technologies AGInventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lüpke, Jochen Müller, Peter Pöchmüller, Michael Schittenhelm
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Patent number: 6721904Abstract: The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.Type: GrantFiled: July 18, 2001Date of Patent: April 13, 2004Assignee: Infineon Technologies AGInventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lüpke, Jochen Müller, Peter Pöchmüller, Michael Schittenhelm
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Patent number: 6556492Abstract: The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.Type: GrantFiled: July 18, 2001Date of Patent: April 29, 2003Assignee: Infineon Technologies AGInventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lüpke, Jochen Müller, Peter Pöchmüller, Michael Schittenhelm
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Patent number: 6535007Abstract: A component holder for testing electronic components having a carrier, at least one component socket arranged on the carrier and having a group of component contacts to accommodate and make contact with a component, and at least one group of adapter contacts, which are arranged in a predefined standard arrangement on the carrier and are connected to the component contacts.Type: GrantFiled: May 10, 2001Date of Patent: March 18, 2003Assignee: Infineon Technologies AGInventors: Hermann Haas, Jens Lüpke
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Patent number: 6515319Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.Type: GrantFiled: May 18, 2001Date of Patent: February 4, 2003Assignee: Infineon Technologies AGInventors: Dietrich Widmann, Armin Wieder, Justus Kuhn, Jens Lüpke, Jochen Müller, Peter Pochmüller, Michael Schittenhelm
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Publication number: 20030005361Abstract: Test circuit for testing a synchronous memory circuit Test circuit for testing a synchronous memory circuit (3) having a frequency multiplication circuit (4) which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor in order to produce a high-frequency clock signal for the synchronous memory chip (3) to be tested, a test data generator (16) which produces test data on the basis of data control signals received from the external test unit (2) and outputs them to a data output driver (14) in order to write them to the synchronous memory circuit (3) to be tested, a first signal delay circuit (19) for delaying the test data which are output by the test data generator (16) by an adjustable first delay time, a second signal delay circuit (24) for delaying data which are read out of the synchronous memory circuit (3) to be tested and are received by a data input driver (15) in the test circuit (1) by an adjustable second delType: ApplicationFiled: March 26, 2002Publication date: January 2, 2003Inventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lupke, Peter Poechmuller, Jochen Mueller, Michael Schittenhelm
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Publication number: 20020160558Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.Type: ApplicationFiled: July 18, 2001Publication date: October 31, 2002Inventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lupke, Jochen Muller, Peter Pochmuller, Michael Schittenhelm
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Publication number: 20020070748Abstract: A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.Type: ApplicationFiled: July 18, 2001Publication date: June 13, 2002Inventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lupke, Jochen Muller, Peter Pochmuller, Michael Schittenhelm
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Patent number: 6396752Abstract: The memory cells with floating gates are tested by applying voltage surges to the source or the drain of a selection transistor.Type: GrantFiled: January 26, 2001Date of Patent: May 28, 2002Assignee: Infineon Technologies AGInventors: Jens Lüpke, Peter Pöchmüller
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Publication number: 20020014669Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.Type: ApplicationFiled: May 18, 2001Publication date: February 7, 2002Inventors: Dietrich Widmann, Helga Widmann, Armin Wieder, Justus Kuhn, Jens Lupke, Jochen Muller, Peter Pochmuller, Michael Schittenhelm
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Publication number: 20020012283Abstract: The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.Type: ApplicationFiled: July 18, 2001Publication date: January 31, 2002Inventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lupke, Jochen Muller, Peter Pochmuller, Michael Schittenhelm
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Publication number: 20020012286Abstract: The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.Type: ApplicationFiled: July 18, 2001Publication date: January 31, 2002Inventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lupke, Jochen Muller, Peter Pochmuller, Michael Schittenhelm
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Publication number: 20020010878Abstract: A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.Type: ApplicationFiled: July 18, 2001Publication date: January 24, 2002Inventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lupke, Jochen Muller, Peter Pochmuller, Michael Schittenhelm
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Publication number: 20020010877Abstract: The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.Type: ApplicationFiled: July 18, 2001Publication date: January 24, 2002Inventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lupke, Jochen Muller, Peter Pochmuller, Michael Schittenhelm
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Publication number: 20020009007Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.Type: ApplicationFiled: July 18, 2001Publication date: January 24, 2002Inventors: Wolfgang Ernst, Gunnar Krause, Justus Kuhn, Jens Lupke, Jochen Muller, Peter Pochmuller, Michael Schittenhelm