Patents by Inventor Jens Peter Konrath
Jens Peter Konrath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136406Abstract: A silicon carbide device includes: a transistor cell having a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; at least one source region of a first conductivity type in contact with the first gate sidewall; and a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. No source regions of the first conductivity type are in contact with a second gate sidewall of the gate structure.Type: ApplicationFiled: December 28, 2023Publication date: April 25, 2024Inventors: Caspar Leendertz, Thomas Basler, Paul Ellinghaus, Rudolf Elpelt, Michael Hell, Jens Peter Konrath, Shiqin Niu, Dethard Peters, Konrad Schraml, Bernd Leonhard Zippelius
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Publication number: 20240105832Abstract: A field effect transistor (FET) is proposed. The FET includes a transistor cell area in a silicon carbide (SiC) semiconductor body. An edge termination area surrounds the transistor cell area. A source contact is arranged over a first surface of the SiC semiconductor body. A drain contact is arranged on a second surface of the SiC semiconductor body. The FET further includes a drift region of a first conductivity type between the first surface and the second surface. Along a lateral direction, a net doping concentration in the drift region is larger in the transistor cell area than in the edge termination area.Type: ApplicationFiled: September 22, 2023Publication date: March 28, 2024Inventors: Thomas Ralf SIEMIENIEC, Hans-Joachim SCHULZE, Jens Peter KONRATH
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Patent number: 11888032Abstract: A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.Type: GrantFiled: December 2, 2022Date of Patent: January 30, 2024Assignee: Infineon Technologies AGInventors: Caspar Leendertz, Thomas Basler, Paul Ellinghaus, Rudolf Elpelt, Michael Hell, Jens Peter Konrath, Shiqin Niu, Dethard Peters, Konrad Schraml, Bernd Leonhard Zippelius
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Patent number: 11854926Abstract: A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.Type: GrantFiled: September 22, 2021Date of Patent: December 26, 2023Assignee: Infineon Technologies AGInventors: Jens Peter Konrath, Christian Hecht, Roland Rupp, Andre Kabakow
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Patent number: 11842938Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.Type: GrantFiled: November 30, 2021Date of Patent: December 12, 2023Assignee: Infineon Technologies AGInventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Publication number: 20230317797Abstract: A wide band gap semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface along a vertical direction. The semiconductor device further includes a first region of a first conductivity type adjoining at least partially the first surface, a drift region of a second conductivity type, a highly doped second region adjoining the second surface, and a buffer region of the second conductivity type arranged between the drift region and the highly doped second region. A vertical profile of a doping concentration of the buffer region includes at least one step in a first section and is increasing approximately exponentially toward the second surface in a second section. The first section is arranged between the second section and the highly doped second region.Type: ApplicationFiled: March 22, 2023Publication date: October 5, 2023Inventors: Hans-Joachim Schulze, Rudolf Elpelt, Jens Peter Konrath, Konrad Schraml
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Publication number: 20230299147Abstract: Disclosed is a method that includes: measuring at least one characteristic of a superjunction region of a SiC superjunction device, wherein the superjunction region is arranged in a semiconductor body and comprises a plurality of first regions of a first doping type and a plurality of second regions of a second doping type complementary to the first doping type; and generating dopant like defects of one doping type in the superjunction region in a doping process. At least one parameter of the doping process is adjusted dependent on the at least one measured characteristic. The doping process includes an implantation process in which particles are implanted into the semiconductor body to form crystal defects in the semiconductor body in the superjunction region, and an annealing process in order to form the dopant like defects based on the crystal defects.Type: ApplicationFiled: March 15, 2023Publication date: September 21, 2023Inventors: Moriz JELINEK, Jens Peter KONRATH, Hans-Joachim SCHULZE, Andre Rainer STEGNER
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Patent number: 11677023Abstract: A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a first trench is formed in a silicon carbide layer. A second trench is formed in the silicon carbide layer to define a mesa in the silicon carbide layer between the first trench and the second trench. A first doped semiconductor material is formed in the first trench and a second doped semiconductor material is formed in the second trench. A third doped semiconductor material is formed over the mesa to define a heterojunction at an interface between the third doped semiconductor material and the mesa.Type: GrantFiled: May 4, 2021Date of Patent: June 13, 2023Assignee: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Jens Peter Konrath, Georg Pfusterschmied, Gregor Pobegen, Ulrich Schmid, Fabian Triendl
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Publication number: 20230094032Abstract: A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.Type: ApplicationFiled: December 2, 2022Publication date: March 30, 2023Inventors: Caspar Leendertz, Thomas Basler, Paul Ellinghaus, Rudolf Elpelt, Michael Hell, Jens Peter Konrath, Shiqin Niu, Dethard Peters, Konrad Schraml, Bernd Leonhard Zippelius
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Patent number: 11552173Abstract: A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.Type: GrantFiled: August 6, 2020Date of Patent: January 10, 2023Assignee: Infineon Technologies AGInventors: Caspar Leendertz, Thomas Basler, Paul Ellinghaus, Rudolf Elpelt, Michael Hell, Jens Peter Konrath, Shiqin Niu, Dethard Peters, Konrad Schraml, Bernd Leonhard Zippelius
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Publication number: 20220359748Abstract: A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a first trench is formed in a silicon carbide layer. A second trench is formed in the silicon carbide layer to define a mesa in the silicon carbide layer between the first trench and the second trench. A first doped semiconductor material is formed in the first trench and a second doped semiconductor material is formed in the second trench. A third doped semiconductor material is formed over the mesa to define a heterojunction at an interface between the third doped semiconductor material and the mesa.Type: ApplicationFiled: May 4, 2021Publication date: November 10, 2022Inventors: Jens Peter KONRATH, Georg Pfusterschmied, Gregor Pobegen, Ulrich Schmid, Fabian Triendl
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Patent number: 11380756Abstract: A silicon carbide device includes a silicon carbide body including a source region of a first conductivity type, a cathode region of the first conductivity type and separation regions of a second conductivity type. A stripe-shaped gate structure extends along a first direction and adjoins the source region and the separation regions. The silicon carbide device includes a first load electrode. Along the first direction, the cathode region is between two separation regions of the separation regions and at least one separation region of the separation regions is between the cathode region and the source region. The source region and the first load electrode form an ohmic contact. The first load electrode and the cathode region form a Schottky contact.Type: GrantFiled: January 3, 2020Date of Patent: July 5, 2022Assignee: INFINEON TECHNOLOGIES AGInventors: Caspar Leendertz, Rudolf Elpelt, Romain Esteve, Thomas Ganner, Jens Peter Konrath, Larissa Wehrhahn-Kilian
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Publication number: 20220199800Abstract: A semiconductor device includes a silicon carbide (SiC) drift zone over a SiC field stop zone and/or a SiC semiconductor substrate. A concentration of Z1/2 defects in the SiC drift zone is at least one order of magnitude smaller than in the SiC field stop zone and/or the SiC semiconductor substrate. Separately or in combination, a concentration of Z1/2 defects in a part of the SiC drift zone is at least one order of magnitude smaller than in another part of the drift zone.Type: ApplicationFiled: March 10, 2022Publication date: June 23, 2022Inventors: Hans-Joachim Schulze, Jens Peter Konrath, Andre Rainer Stegner, Helmut Strack
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Patent number: 11322596Abstract: An embodiment of a semiconductor device comprises a SiC semiconductor body, a gate dielectric and a gate electrode. A first trench extends from a first surface of the SiC semiconductor body into the SiC semiconductor body. A junction material is in the first trench, wherein the junction material and the SiC semiconductor body form a diode.Type: GrantFiled: August 23, 2019Date of Patent: May 3, 2022Assignee: INFINEON TECHNOLOGIES AGInventors: Jens Peter Konrath, Caspar Leendertz, Larissa Wehrhahn-Kilian
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Patent number: 11302795Abstract: A method of manufacturing a semiconductor device is proposed. A silicon carbide, SiC, semiconductor body is provided. Ions are introduced into the SiC semiconductor body through a first surface of the SiC semiconductor body by at least one ion implantation process. Thereafter, a SiC device layer is formed on the first surface of the SiC semiconductor body. Semiconductor device elements are formed in or over the SiC device layer.Type: GrantFiled: July 10, 2020Date of Patent: April 12, 2022Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Jens Peter Konrath, Andre Rainer Stegner, Helmut Strack
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Publication number: 20220093483Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.Type: ApplicationFiled: November 30, 2021Publication date: March 24, 2022Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Publication number: 20220005742Abstract: A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Inventors: Jens Peter Konrath, Christian Hecht, Roland Rupp, Andre Kabakow
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Patent number: 11217500Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.Type: GrantFiled: April 9, 2019Date of Patent: January 4, 2022Assignee: Infineon Technologies AGInventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Patent number: 11211303Abstract: An embodiment of a semiconductor device includes a semiconductor body having a first main surface. The semiconductor body includes an active device area and an edge termination area at least partly surrounding the active device area. The semiconductor device further includes a contact electrode on the first main surface and electrically connected to the active device area. The semiconductor device further includes a passivation structure on the edge termination area and laterally extending into the active device area. The semiconductor device further includes an encapsulation structure on the passivation structure and covering a first edge of the passivation structure above the contact electrode.Type: GrantFiled: December 3, 2019Date of Patent: December 28, 2021Assignee: Infineon Technologies AGInventors: Jens Peter Konrath, Jochen Hilsenbeck, Dethard Peters, Paul Salmen, Tobias Schmidutz, Vice Sodan, Christian Stahlhut, Juergen Steinbrenner, Bernd Zippelius
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Patent number: 11158557Abstract: A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.Type: GrantFiled: April 25, 2019Date of Patent: October 26, 2021Assignee: Infineon Technologies AGInventors: Jens Peter Konrath, Christian Hecht, Roland Rupp, Andre Kabakow