Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.

Abstract: Embodiments relate to memory devices and methods for firmly programming at least a portion of a plurality of electronically programmable and erasable nonvolatile memory cells in a processing of the nonvolatile memory devices.

Abstract: Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation.

Abstract: Systems and methods related to a memory device are provided. The systems and methods include using at least one driver with predetermined reduced driving capability to drive at least one of the memory elements of the memory device in a reliable detection algorithm. The at least one driver has reduced driving capability compared to a driver used for standard read access. The reliable detection algorithm can include detecting failing memory elements on a respective reading current diverging from an expected or expectable reading current.

Abstract: The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.

Abstract: A method is described for transmitting signals on a pair of lines, whereby the signals pass alternately from a low level to a high level. The signals on one line of the pair transmit a complementary level of signals to the other line of the pair, whereby signal drivers are used in a manner to affect an exchange in the levels of the transmitted signals. First, the signal drivers that send complementary levels of signals to the two lines are isolated from the lines. Second, the lines are short-circuited so that an identical intermediary potential between the low-level and the high-level signal, is applied. Third, the short-circuit is removed and the signal drivers are connected so that inversely complementary levels of signals can be sent to both lines.

Abstract: An integrated circuit having capacitive elements for smoothing a supply voltage is described. In this case, at least one additional metal electrode, which is configured as a high frequency-optimized capacitance and is distinguished by an extremely low sheet resistance, is connected in parallel with the MOS capacitances. By connecting the areally highly effective MOS capacitance, which, however, is connected with a somewhat higher impedance, in parallel with areally less effective metal capacitances, which, however, are connected to the supply voltage in a very low-impedance manner, it is possible to obtain broadband buffering and thus decoupling of high-frequency interference signals. Very high-frequency interference components are attenuated on the chip and do not pass into the system surrounding the integrated circuit.

Abstract: A method is described for transmitting signals on a pair of lines, whereby the signals pass alternately from a low level to a high level. The signals on one line of the pair transmit a complementary level of signals to the other line of the pair, whereby signal drivers are used in a manner to affect an exchange in the levels of the transmitted signals. First, the signal drivers that send complementary levels of signals to the two lines are isolated from the lines. Second, the lines are short-circuited so that an identical intermediary potential between the low-level and the high-level signal, is applied. Third, the short-circuit is removed and the signal drivers are connected so that inversely complementary levels of signals can be sent to both lines.

Abstract: A configuration and a method for matching output drivers of integrated circuits to specified conditions include parameters to be taken into account when matching output drivers and/or control signals based on the parameters for matching the output drivers, to be provided in digital form. The configuration and method may additionally or alternatively perform matching by taking into account a level or waveform of a supply voltage of an integrated circuit and/or a technology used in the integrated circuit and/or technical data on a load to be driven and/or demands placed on the output drivers by the load to be driven.

Abstract: An integrated circuit having capacitive elements for smoothing a supply voltage is described. In this case, at least one additional metal electrode, which is configured as a high frequency-optimized capacitance and is distinguished by an extremely low sheet resistance, is connected in parallel with the MOS capacitances. By connecting the areally highly effective MOS capacitance, which, however, is connected with a somewhat higher impedance, in parallel with areally less effective metal capacitances, which, however, are connected to the supply voltage in a very low-impedance manner, it is possible to obtain broadband buffering and thus decoupling of high-frequency interference signals. Very high-frequency interference components are attenuated on the chip and do not pass into the system surrounding the integrated circuit.