Abstract: A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.

Abstract: A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.

Abstract: A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.

Abstract: A non-volatile semiconductor memory (30) comprising a semiconductor substrate (1) and a plurality of memory cells (19) and methods for manufacturing such a memory is provided. Each memory cell (19) comprises a charge-trapping element (5), a gate stack (20), nitride spacers (10) and electrically insulating elements (21). The charge-trapping element (5) is arranged on the semiconductor substrate (1) and comprises a nitride layer (3) sandwiched between a bottom oxide layer (2) and a top oxide layer (4), the charge-trapping element (5) having two lateral sidewalls (24) opposed to one another. The gate stack (20) is arranged on top of the charge-trapping element (5), the gate stack having two lateral sidewalls (25) opposing one another. The electrically insulating elements (21) are disposed at opposing sidewalls (24) of the charge-trapping element (5) and cover the sidewalls (24) of the charge-trapping element (5).

Abstract: A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.

Abstract: A device for thermally treating semiconductor wafers having at least one silicon layer to be oxidized and a metal layer, preferably a tungsten layer, which is not to be oxidized. The inventive device comprises the following: at least one radiation source; a treatment chamber receiving the substrate, with at least one wall part located adjacent to the radiation sources and which is substantially transparent for the radiation of said radiation source; and at least one cover plate between the substrate and the wall part of the treatment chamber located adjacent to the radiation sources, the dimensions of said cover plate being selected such that it fully covers the transparent wall part of the treatment chamber in relation to the substrate in order to prevent material, comprising a metal, metal oxide or metal hydroxide such as tungsten, tungsten oxide or tungsten hydroxide, from said substrate from becoming deposited on or evaporating onto the transparent wall part of the treatment chamber.

Abstract: A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.

Abstract: An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.

Abstract: An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.

Abstract: The surfaces of wordline stacks and intermediate areas of a main substrate surface are covered with an oxynitride liner. Either sidewall spacers of BPSG are formed or a further liner of nitride is deposited and spacers of oxide are formed. These spacers are used in a peripheral area of addressing circuitry to implant doped source/drain regions. The oxynitride reduces the stress between the nitride and the semiconductor material and prevents charge carriers from penetrating out of a memory layer of nitride into the liner.

Abstract: A non-volatile semiconductor memory (30) comprising a semiconductor substrate (1) and a plurality of memory cells (19) and methods for manufacturing such a memory is provided. Each memory cell (19) comprises a charge-trapping element (5), a gate stack (20), nitride spacers (10) and electrically insulating elements (21). The charge-trapping element (5) is arranged on the semiconductor substrate (1) and comprises a nitride layer (3) sandwiched between a bottom oxide layer (2) and a top oxide layer (4), the charge-trapping element (5) having two lateral sidewalls (24) opposed to one another. The gate stack (20) is arranged on top of the charge-trappinig element (5), the gate stack having two lateral sidewalls (25) opposing one another. The electrically insulating elements (21) are disposed at opposing sidewalls (24) of the charge-trapping element (5) and cover the sidewalls (24) of the charge-trapping element (5).

Abstract: During a selective oxidation of gate structures that includes a polycrystalline silicon layer and a tungsten layer, which is known per se, a vapor deposition of tungsten oxide is prevented or at least greatly reduced by a special process. The gate structure is acted on by a hydrogen-containing, nonaqueous inert gas before and, if appropriate, after a treatment step with a hydrogen/water mixture.

Abstract: A device for thermally treating semiconductor wafers having at least one silicon layer to be oxidized and a metal layer, preferably a tungsten layer, which is not to be oxidized. The inventive device comprises the following: at least one radiation source; a treatment chamber receiving the substrate, with at least one wall part located adjacent to the radiation sources and which is substantially transparent for the radiation of said radiation source; and at least one cover plate between the substrate and the wall part of the treatment chamber located adjacent to the radiation sources, the dimensions of said cover plate being selected such that it fully covers the transparent wall part of the treatment chamber in relation to the substrate in order to prevent material, comprising a metal, metal oxide or metal hydroxide such as tungsten, tungsten oxide or tungsten hydroxide, from said substrate from becoming deposited on or evaporating onto the transparent wall part of the treatment chamber.

Abstract: A semiconductor device is formed by forming a plurality of trenches in a semiconductor body. The trenches alternate between active trenches and isolation trenches with the isolation trenches being deeper than the active trenches. The semiconductor body is doped so that a top surface of the semiconductor body adjacent each active trench and a floor of each active trench is doped. Memory cell components are formed in each active trench. The memory cell components include a gate electrode and a charge-trapping layer disposed between the gate electrode and a sidewall of the trench. The charge-trapping layer includes a memory layer disposed between first and second limiting layers. Bitlines are formed over the semiconductor body and electrically coupled doped regions adjacent to the top surface of the semiconductor body adjacent the active trenches. Bitline contacts are coupled to the bitlines.

Abstract: Electrically conductive material is introduced into interspaces between the word lines (2) and is partially removed using a mask (6) in such a way that residual portions (7) of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (15). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.

Abstract: A semiconductor device comprises a transistor body of boron doped semiconductor substrate and a conterminous isolating area formed of insulating material, wherein an oxy-nitride layer is between the transistor body and the isolating area. This invention can be used in a transistor body for example in an NROM cell.

Abstract: A method for manufacturing a semiconductor device includes forming a storage layer over a semiconductor body. The storage layer includes a first boundary layer, an intermediate storage layer and a second boundary layer. The storage layer is patterned so that at least some of the storage layer is removed from over a first portion of the semiconductor body and some of the storage layer is removed from over a second portion of the semiconductor body. The first portion of the semiconductor body is doped and the second portion of the semiconductor body is etched.

Abstract: Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.

Abstract: Isolation trench arrangement, which isolates adjacent semiconductor structures (1), (2), an isolation trench (3) being formed in such a way that it penetrates from a substrate surface into the substrate volume (0) and has at least one insulating substance (20) and at least one conductive substance (21), and the conductive substance (21) is electrically conductively connected to the substrate (0) via an electrically conductive connection (22).

Abstract: A method is provided for operating an electrical writable and erasable memory cell, which has a channel region (2) that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.