Patents by Inventor Jeong-do Ryu

Jeong-do Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100035425
    Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
    Type: Application
    Filed: August 6, 2009
    Publication date: February 11, 2010
    Inventors: Jeong Do Ryu, Si-Young Choi, Yu-Gyun Shin, Tai-Su Park, Dong-Chan Kim, Jong-Ryeol Yoo, Seong-Hoon Jeong, Jong-Hoon Kang
  • Publication number: 20100025749
    Abstract: A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region.
    Type: Application
    Filed: August 3, 2009
    Publication date: February 4, 2010
    Inventors: Jong-Ryeol Yoo, Tai-Su Park, Jong-Hoon Kang, Dong-Chan Kim, Jeong-Do Ryu, Seong-Hoon Jeong, Si-Young Choi, Yu-Gyun Shin
  • Patent number: 7498213
    Abstract: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: March 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Jin Kim, Young-Wook Park, Jeong-Do Ryu
  • Publication number: 20070004211
    Abstract: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate.
    Type: Application
    Filed: September 8, 2006
    Publication date: January 4, 2007
    Inventors: Won Kim, Young-Wook Park, Jeong-Do Ryu
  • Patent number: 7129174
    Abstract: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: October 31, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Jin Kim, Young-Wook Park, Jeong-Do Ryu
  • Publication number: 20050285162
    Abstract: Methods of forming a semiconductor device having stacked structures include forming a first semiconductor structure on a substrate and forming a first interlayer insulating layer on the substrate. The first interlayer insulating layer has a substantially level upper face. A semiconductor layer is formed on the first interlayer insulating layer and a first gate insulation layer is formed on the semiconductor layer at a processing temperature selected to control damage to the first semiconductor structure. A second semiconductor structure is formed on the first gate insulation layer.
    Type: Application
    Filed: June 23, 2005
    Publication date: December 29, 2005
    Inventors: Chul-Sung Kim, Jin-Hwa Heo, Yu-Gyun Shin, Bon-Young Koo, Dong-Chan Kim, Jeong-Do Ryu
  • Patent number: 6930062
    Abstract: A method of forming an oxide layer on a semiconductor substrate includes thermally oxidizing a surface of the substrate to form an oxide layer on the substrate, and then exposing the oxide layer to an ambient including predominantly oxygen radicals to thereby thicken the oxide layer. Related methods of fabricating a recessed gate transistor are also discussed.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: August 16, 2005
    Assignee: Samsung Electronics Co., Inc.
    Inventors: Sang-Jin Hyun, Yu-Gyun Shin, Bon-Young Koo, Sug-Hun Hong, Taek-Soo Jeon, Jeong-do Ryu
  • Publication number: 20050003679
    Abstract: A method of forming an oxide layer on a semiconductor substrate includes thermally oxidizing a surface of the substrate to form an oxide layer on the substrate, and then exposing the oxide layer to an ambient including predominantly oxygen radicals to thereby thicken the oxide layer. Related methods of fabricating a recessed gate transistor are also discussed.
    Type: Application
    Filed: May 21, 2004
    Publication date: January 6, 2005
    Inventors: Sang-Jin Hyun, Yu-Gyun Shin, Bon-Young Koo, Sug-Hun Hong, Taek-Soo Jeon, Jeong-do Ryu
  • Publication number: 20040241946
    Abstract: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate.
    Type: Application
    Filed: March 23, 2004
    Publication date: December 2, 2004
    Inventors: Won-Jin Kim, Young-Wook Park, Jeong-Do Ryu