Abstract: A semiconductor device includes an interface pad, and an antenna formed to surround the interface pad. The semiconductor device may further include a buffer configured to receive a first input signal applied to the interface pad, a driver configured to output a first output signal to the interface pad a receiver configured to receive a second input signal transferred to the antenna, and a transmitter configured to output a second output signal to the antenna.

Abstract: A device for storing error information of a memory device includes a plurality of parent memories and a plurality of child memories. Each of the parent memories stores a row address and a column address of one defective cell. Each of the child memories stores a column address of a defective cell, having a row address identical to a row address stored in the corresponding parent memory, or a row address of a defective cell, having a column address identical to a column address stored in the corresponding parent memory. Herein, each of the parent memories stores information about information about whether a row repair must be performed to repair a defective cell stored in the parent memory and information about whether a column repair must be performed to repair a defective cell stored in the parent memory.

Abstract: A device for repair analysis includes a selection unit and an analysis unit. The selection unit is configured to select a part of the row addresses of a plurality of spare pivot fault cells and a part of the column addresses of the spare pivot fault cells in response to a control code. The analysis unit is configured to generate an analysis signal indicating whether row addresses of a plurality of non-spare pivot fault cells are included in selected row addresses and column addresses of the non-spare pivot fault cells are included in selected column addresses.

Abstract: A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.

Abstract: A method of correcting bonding coordinates according to locations of a die and leads loaded for bonding is provided. The method includes searching for locations of die recognition areas and lead recognition areas, comparing the detected locations of the recognition areas, and correcting bonding coordinates of the die and the leads according to the result obtained by the comparison; and if a search for the locations of the die recognition areas fails, searching for reference bond pads, comparing locations of the detected reference bond pads with setting locations, and correcting bonding coordinates of a die and leads to be bonded according to the result obtained by the comparison.

Abstract: A method of correcting bonding coordinates according to locations of a die and leads loaded for bonding is provided. The method includes searching for locations of die recognition areas and lead recognition areas, comparing the detected locations of the recognition areas, and correcting bonding coordinates of the die and the leads according to the result obtained by the comparison; and if a search for the locations of the die recognition areas fails, searching for reference bond pads, comparing locations of the detected reference bond pads with setting locations, and correcting bonding coordinates of a die and leads to be bonded according to the result obtained by the comparison.

Abstract: A method for manufacturing a ceramic resonator is disclosed. The method comprises the steps of forming a ceramic piezoelectric device, a capacitor chip and a lead frame, assembling the piezoelectric device and the capacitor chip into the lead frame, and molding the assembled chip by using epoxy resin. A process for making the capacitor includes the steps of cutting a ceramic wafer into a plurality of sub-wafers, printing electrodes on one face of the sub-wafer in a dual-striped form, drying the sub-wafer thus printed, printing another electrode on a central part of another face of the sub-wafer so as to be overlapped with the electrodes of the one face of the sub-wafer, drying the sub-wafer thus printed, baking the sub-wafer thus dried; and cutting the sub-wafer thus baked into a plurality of capacitors.

Abstract: A ferroelectric memory device manufacturing method capable of improving topology between a ferroelectric memory device and a logic device. The method for manufacturing the ferroelectric memory device includes steps of: a) forming an insulating layer on a semiconductor substrate; b) opening a capacitor region by selectively patterning the insulating layer; c) forming a bottom electrode in the opened capacitor region by using a chemical vapor deposition (CVD) method; d) forming a ferroelectric layer on a subsequent insulating layer including the bottom electrode; e) filling the ferroelectric layer on the capacitor region to a same height as that of the subsequent insulating layer surface; and f) forming a top electrode on the ferroelectric layer.

Abstract: A high frequency resonator and a manufacturing method therefor are disclosed. The method for manufacturing a ceramic resonator includes the step of forming a ceramic piezoelectric device, a capacitor chip and a lead frame. Then the piezoelectric device and the capacitor chip are assembled into the lead frame, and the assembled chip is molded by using epoxy resin. The process for making the capacitor includes the step of cutting a ceramic wafer into a plurality of sub-wafers. Then electrodes are printed on one face of the sub-wafer in a dual-striped form, and a drying is carried out on the sub-wafer thus printed. Then another electrode is printed on a central part of the opposite face of the sub-wafer in such a manner as to be overlapped with the electrodes of the one face of the sub-wafer. Then the sub-wafer is dried. Then a baking is carried out on the sub-wafer thus dried, and the sub-wafer thus baked is cut into a plurality of capacitor chips.