Abstract: An LCD device includes a liquid crystal panel; a first polarizer attached to a first surface of the liquid crystal panel and including a first polarizing film, first and second optical compensation films disposed on one surface of the first polarizing film, and a phase retardation film, a protective film and a functional film disposed on another surface of the first polarizing film; and a second polarizer attached to a second surface of the liquid crystal panel and including a second polarizing film, an inner protective film disposed on one surface of the second polarizing film, and an outer protective film disposed on another surface of the second polarizing film, wherein the first polarizing film is disposed between the phase retardation film and the liquid crystal panel, and the phase retardation film has a retardation value of ?/4.

Abstract: A LCD device includes a liquid crystal panel, an upper polarizing plate disposed above the liquid crystal panel, a lower polarizing plate disposed under the liquid crystal panel, a retardation film formed on a polarization layer of the upper polarizing plate, and a liquid crystal polarizing film attached to the retardation film. Since the LCD device uses a polarized liquid crystal film that is formed of a liquid crystal films to perform a mirror function, the deterioration in the image quality due to the surface unevenness is improved. Also, since the LCD device uses a polarized liquid crystal film to enable the display function and the mirror function of the LCD device, a user who wears polarized sunglasses can detect the mirror function.

Abstract: A liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel which has a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of liquid crystal cells that are defined by the data lines and the gate lines; a first data driver disposed at an upper side of the liquid crystal display panel to supply data to odd-numbered data lines; a second data driver disposed at a lower side of the liquid crystal display panel to supply data to even-numbered data lines; a first gate driver disposed at a left side of the liquid crystal display panel to supply a scan pulse to odd-numbered gate lines; and a second gate driver disposed at a right side of the liquid crystal display panel to supply a scan pulse to even-numbered gate lines, and wherein at least any one of the data lines and the gate lines has a line width that varies along its length.

Abstract: A back light structure includes lamps for supplying light to an LCD panel, and a micro-lens formed on over or below the lamps, the micro-lens having a plurality of concave portions or convex portions.

Abstract: An array substrate for an in-plane switching mode liquid crystal display devices includes: a substrate; a gate line and a data line on the substrate, the gate line crossing the data line to define a pixel region; a common line parallel to the gate line; a thin film transistor connected to the gate line and the data line; a plurality of common electrodes extending from the common line, and a plurality of pixel electrodes alternating with the plurality of common electrodes, wherein a gap distance is defined as a width of a block by the adjacent common and pixel electrode in the pixel region, and at least one gap distance is different from the other gap distances.

Abstract: A liquid crystal display device includes a first pixel and a second pixel. The first pixel includes a first thin film transistor having a first channel W/L (width/length) ratio and a first gate-drain parasitic capacitance. The second pixel includes a second thin film transistor that is disposed at a different relative position than the first thin film transistor. The second thin film transistor has a second channel W/L (width/length) ratio and a second gate-drain parasitic capacitance. The first and second channel W/L ratios are substantially the same, and the first and second gate-drain parasitic capacitances are different from each other such that the first and second pixels have substantially the same common voltages.

Abstract: A liquid crystal display device includes a first pixel and a second pixel. The first pixel includes a first thin film transistor having a first channel W/L (width/length) ratio and a first gate-drain parasitic capacitance. The second pixel includes a second thin film transistor that is disposed at a different relative position than the first thin film transistor. The second thin film transistor has a second channel W/L (width/length) ratio and a second gate-drain parasitic capacitance. The first and second channel W/L ratios are substantially the same, and the first and second gate-drain parasitic capacitances are different from each other such that the first and second pixels have substantially the same common voltages.

Abstract: An array substrate for an in-plane switching mode liquid crystal display devices includes: a substrate; a gate line and a data line on the substrate, the gate line crossing the data line to define a pixel region; a common line parallel to the gate line; a thin film transistor connected to the gate line and the data line; a plurality of common electrodes extending from the common line, and a plurality of pixel electrodes alternating with the plurality of common electrodes, wherein a gap distance is defined as a width of a block by the adjacent common and pixel electrode in the pixel region, and at least one gap distance is different from the other gap distances.

Abstract: An off-line feed rate scheduling method of a CNC machining process includes selecting a constraint variable and inputting a reference value related to the constraint variable; estimating a cutting configuration where a maximum constraint variable value (CVV) occurs through ME Z-map modeling; receiving the estimated cutting configuration and estimating a specific rotation angle (?s) where the maximum constraint variable value occurs through constraint variable modeling; calculating a feed rate that satisfies the reference value of the constraint variable at the estimated specific rotation angle; and applying the calculated feed rate to the NC code. Cutting force or machined surface error may be selected as a constraint variable depending on machining conditions.

Abstract: A back light structure includes lamps for supplying light to an LCD panel, and a micro-lens formed on over or below the lamps, the micro-lens having a plurality of concave portions or convex portions.

Abstract: This invention discloses an optical module with multiplexer for a remote of an IMT-2000 digital optical repeater. The functions of an optical transmitting part of the digital optical repeater according to the present invention is data donation through a forward link, data add/drop in each sector, data summing in respective sectors and data transmission through a reverse link. This invention discloses an optical module with multiplexer that is capable of implementing the optical transmitting part's function effectively by using a signal framing, scrambling, add/drop and PLL circuits with high Q value.

Abstract: An off-line feed rate scheduling method of a CNC machining process includes selecting a constraint variable and inputting a reference value related to the constraint variable; estimating a cutting configuration where a maximum constraint variable value (CVV) occurs through ME Z-map modeling; receiving the estimated cutting configuration and estimating a specific rotation angle (?s) where the maximum constraint variable value occurs through constraint variable modeling; calculating a feed rate that satisfies the reference value of the constraint variable at the estimated specific rotation angle; and applying the calculated feed rate to the NC code. Cutting force or machined surface error may be selected as a constraint variable depending on machining conditions.

Abstract: A clock signal generating apparatus for a data communication channel is disclosed which includes a first clock signal generating unit for receiving an external input clock signal and a frame position informing signal and outputting a predetermined cycle first clock signal and a first timing signal, a second clock signal generating unit for receiving the first clock signal and the first timing signal and externally outputting a first offset signal, a second timing signal, and a predetermined cycle second clock signal, respectively, and a third clock signal generating unit for receiving the first clock signal and the first timing signal and externally outputting a second offset signal, a third timing signal and a predetermined cycle third clock signal, respectively, for thereby implementing a reliable serial/parallel conversion, extraction and insertion of a data by generating a stable clock and timing signal using a simple circuit and supplying a stable clock signal for matching with an external apparatus for