Abstract: A semiconductor device may include a gate structure including stacked local lines and a multi-step structure, wherein the multi-step structure defines pads of the local lines, channel patterns respectively disposed over the pads, a block word line disposed over the channel patterns and extending along a profile of the multi-step structure, and first contact plugs passing through the channel patterns and respectively connecting the channel patterns and the local lines.

Abstract: The present invention relates to a bispecific humanized single domain antibody targeting both PD-L1 and CD47, as well as uses thereof. Specifically, a humanized single domain antibody that binds bispecifically to PD-L1 and CD47, which are immune checkpoint proteins, has been developed, and its efficacy has been confirmed both in vitro and in vivo. Therefore, the bispecific humanized single domain antibody can be effectively used as an immune checkpoint inhibitor for immuno-oncology therapy.

Abstract: The present technology includes a memory device and a method of manufacturing the memory device. The memory device includes a memory block in which first and second connection regions and a cell region between the first and second connection regions are designated, a word line included in the memory block, a first drain selection line included in the memory block and positioned on the word line, a first drain contact contacting the first drain selection line of the first connection region, a second drain contact contacting the first drain selection line of the second connection region, and a first drain voltage supply line commonly contacting the first and second drain contacts.

Abstract: A method of controlling physical properties of an electrolytic copper foil according to one embodiment of the present invention includes: controlling the physical properties of the electrolytic copper foil including elongation, tensile strength and roughness by regulating a surface glossiness of the electrolytic copper foil through addition of a surface glossiness agent. The surface glossiness is regulated within a range of 35 to 400 GU (60°).

Abstract: A semiconductor device, and a method of manufacturing the same, includes a gate stack including a plurality of conductive lines extending in a first horizontal direction, a first slit and a second slit passing through the gate stack in a vertical direction and extending in the first horizontal direction, and a plurality of cell plugs extending in the vertical direction orthogonal to the first horizontal direction in the gate stack between the first slit and the second slit. Each of the first slit and the second slit includes a first portion extending in a diagonal direction between the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, and a second portion extending in the first horizontal direction.

Abstract: The present discloses provides a memory device and a method of operating the memory device. The memory device includes first main plugs formed in a vertical direction over a substrate and arranged in a first direction, second main plugs, third main plugs arranged between the first and second main plugs, the third main plugs adjacent to the first and second main plugs, and bit lines above the first to third main plugs, wherein each of the first to third main plugs includes first and second sub-plugs facing each other, wherein portions of the first and second sub-plugs included in each of the first and third main plugs are coupled to different select lines, and wherein portions of the first and second sub-plugs included in each of the second and third main plugs are coupled to different select lines.

Abstract: A memory device, and a method of manufacturing the same, includes a first select line including a first cell area, a second select line including a second cell area disposed in a first direction from the first cell area, a first separation pattern extending in a second direction intersecting the first direction between the first cell area and the second cell area, second separation patterns extending from both ends of the first separation pattern in the first direction and a third direction opposite the first direction, respectively, and a third separation pattern extending from at least one of the second separation patterns in the second direction, and disposed in a direction opposite the first separation pattern with respect to the at least one second separation pattern.

Abstract: Methods of semiconductor processing may include providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed on a substrate support within the processing region. A layer of silicon-and-nitrogen-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the hydrogen-containing precursor. The methods may include contacting the layer of silicon-and-nitrogen-containing material with plasma effluents of the hydrogen-containing precursor. The contacting may etch a portion of the layer of silicon-and-nitrogen-containing material.

Abstract: A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.

Abstract: A memory device includes: a memory cell array including a plurality of cell plugs; a first slit isolating the memory cell array into a plurality of memory regions, the first slit extending in a first direction; and second slits penetrating the plurality of memory regions, the second slits being arranged to be spaced apart from each other in a second direction intersecting the first direction. Gate lines included in each of the plurality of memory regions may be isolated from each other by the first slit. Each gate line located in the same layer among the gate lines included in each of the plurality of memory regions may extend through a first connection region between the second slits for each corresponding memory region.

Abstract: A display device includes a substrate that includes a display area and a non-display area; a mask support that is disposed in the non-display area of the substrate; a sealant that is disposed in the non-display area of the substrate and is disposed between the mask support and the display area; an insulating layer that is disposed between the sealant and the mask support; and a plurality of grooves that are formed by removing at least a part of the insulating layer.

Abstract: A semiconductor device may include: a first gate structure including a plurality of first conductive layers that are alternately stacked with a plurality of first insulating layers; a second gate structure including a plurality of second conductive layers that are alternately stacked with a plurality of second insulating layers; a third gate structure including third conductive layers that are alternately stacked with a plurality of third insulating layers; and a first contact plug extending into the first gate structure through the third gate structure and the second gate structure, the first contact plug connected to a first of the plurality of first conductive layers, and the first contact plug including a first inflection portion located at an interface between the second gate structure and the third gate structure.

Abstract: A method for manufacturing an electrolytic copper foil according to one embodiment of the present disclosure includes: preparing an electrolyte containing copper ion and nickel ion by dissolving copper (Cu) and nickel (Ni) in sulfuric acid; and forming a copper layer by supplying an electric current to a positive plate and a negative electrode rotating drum disposed apart from each other in the electrolyte. The concentration of the nickel ion is 50 ppm to 350 ppm.

Abstract: The present discloses provides a memory device and a method of operating the memory device. The memory device includes first main plugs formed in a vertical direction over a substrate and arranged in a first direction, second main plugs, third main plugs arranged between the first and second main plugs, the third main plugs adjacent to the first and second main plugs, and bit lines above the first to third main plugs, wherein each of the first to third main plugs includes first and second sub-plugs facing each other, wherein portions of the first and second sub-plugs included in each of the first and third main plugs are coupled to different select lines, and wherein portions of the first and second sub-plugs included in each of the second and third main plugs are coupled to different select lines.

Abstract: An example image forming apparatus includes a power device, a photosensitive drum, a transfer device to remove remaining toner based on a cleaning bias voltage, an optical sensor to detect remaining toner, and a processor to adjust the cleaning bias voltage based on a set offset bias voltage. The processor may change a surface potential of the photosensitive drum to a voltage of a set pattern using the power device, acquire a size ratio of a periodic component based on a frequency of a signal detected from the remaining toner using the optical sensor, and, based on the acquired size ratio of the periodic component being greater than or equal to a set size ratio, adjust the cleaning bias voltage based on an offset bias voltage corresponding to the size ratio of the periodic component and provide the adjusted cleaning bias voltage to the transfer device to remove remaining toner.

Abstract: A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.

Abstract: Provided are an ethylene-propylene-diene monomer (EPDM) copolymer and a method of preparing the same. An EPDM copolymer which has more improved miscibility with inorganic fillers such as carbon black, may further facilitate dispersibility in mixing to further decrease the viscosity of a compound composition, and may provide a compound composition having excellent processability and mechanical properties. A method of preparing the same is also provided.

Abstract: Exemplary methods of semiconductor processing may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include a boron-containing material overlying a carbon-containing material. The methods may include generating plasma effluents of the fluorine-containing precursor. The methods may include contacting the substrate with the plasma effluents of the fluorine-containing precursor. The methods may include removing the boron-containing material from the substrate.

Abstract: Provided is a heating element having a fuse function. The heating element having a fuse function according to an exemplary embodiment of the present invention includes a plurality of heat sources which generate heat when power is applied, a fuse member of which both end portions are physically connected to two heat sources disposed to be spaced apart from each other by a gap to connect the two heat sources in series and which is fused to electrically disconnect the two heat sources when a temperature is higher than or equal to a preset temperature, and an insulating member which surrounds the plurality of heat sources and the fuse member.

Abstract: A display device includes a metal layer disposed on a substrate; a transistor disposed on the metal layer; and a light emitting element electrically connected to the transistor, wherein the transistor includes a semiconductor layer at least partially overlapping the metal layer, the semiconductor layer includes a first region, a second region, and a channel region disposed between the first region and the second region, and the metal layer overlaps the second region and the channel region and is spaced apart from the first region in a plan view.