Patents by Inventor JEONG HYEON PARK

JEONG HYEON PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9871063
    Abstract: A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 16, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Bo Seok Oh, Hee Hwan Ji, Jeong Hyeon Park
  • Publication number: 20180013421
    Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.
    Type: Application
    Filed: December 28, 2016
    Publication date: January 11, 2018
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Jeong Hyeon PARK, Bo Seok OH, Hee Hwan JI
  • Patent number: 8782902
    Abstract: A method of making a bearing includes providing a bearing intermediate, which is unfinished while having an overall shape of a finished bearing product; and repeatedly impacting a surface of the bearing intermediate at one or more ultrasonic frequencies to modify characteristics of the bearing intermediate. The resulting bearing intermediate or finished bearing product includes nano-size grains at or underneath the surface.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: July 22, 2014
    Assignee: Designmecha Co., Ltd.
    Inventors: Young Sik Pyun, Jeong Hyeon Park, Chang Sik Kim, In Ho Cho
  • Publication number: 20100024218
    Abstract: A method of making a bearing includes providing a bearing intermediate, which is unfinished while having an overall shape of a finished bearing product; and repeatedly impacting a surface of the bearing intermediate at one or more ultrasonic frequencies to modify characteristics of the bearing intermediate. The resulting bearing intermediate or finished bearing product includes nano-size grains at or underneath the surface.
    Type: Application
    Filed: October 13, 2009
    Publication date: February 4, 2010
    Applicant: DESIGNMECHA CO., LTD.
    Inventors: YOUNG SIK PYUN, JEONG HYEON PARK, CHANG SIK KIM, IN HO CHO