Patents by Inventor Jeong-Jin Kim
Jeong-Jin Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150129890Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.Type: ApplicationFiled: December 29, 2014Publication date: May 14, 2015Inventors: Hokyun AHN, Jong-Won LIM, Jeong-Jin KIM, Hae Cheon KIM, Jae Kyoung MUN, Eun Soo NAM
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Patent number: 8952422Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.Type: GrantFiled: June 7, 2013Date of Patent: February 10, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Hokyun Ahn, Jong-Won Lim, Jeong-Jin Kim, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8860716Abstract: A method and a 3D display apparatus for processing a stereoscopic image signal in high rate by software while using a least number of hardware components in a portable 3D display apparatus based on a mobile Android platform are provided. This method is suitable for a portable terminal apparatus equipped with a kernel layer directly controlling hardware means including a display panel, and an application/middleware layer controlling the kernel layer to display a motion picture through the hardware means. One or more plane image surfaces are first generated from the application/middleware layer and stored in a first frame buffer. An encoded image signal is decoded under the application/middleware layer to restore a YUV image signal representing a stereoscopic image pair. Subsequently, the YUV image signal is converted into an RGB image signal, and left and right images of the RGB image signal are mixed at the kernel layer.Type: GrantFiled: October 12, 2011Date of Patent: October 14, 2014Assignee: 3D NURI Co., Ltd.Inventors: Jeong Jin Kim, Chul Park
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Publication number: 20140167111Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.Type: ApplicationFiled: June 7, 2013Publication date: June 19, 2014Inventors: Hokyun AHN, Jong-Won Lim, Jeong-Jin Kim, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140159049Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.Type: ApplicationFiled: May 30, 2013Publication date: June 12, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Sang Choon KO, Jae Kyoung Mun, Byoung-Gue Min, Young Rak Park, Hokyun Ahn, Jeong-Jin Kim, Eun Soo Nam
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Publication number: 20130069127Abstract: A method for fabricating a field effect transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a cap layer, an ohmic metal layer and an insulating layer on a substrate; forming multilayered photoresists on the insulating layer; patterning the multilayered photoresists to form a photoresist pattern including a first opening for gate electrode and a second opening for field electrode; etching the insulating layer by using the photoresist pattern as an etching mask so that the insulating layer in the first opening is etched more deeply and the cap layer is exposed through the first opening; etching the cap layer exposed by etching the insulating layer through the first opening to form a gate recess region; and depositing a metal on the gate recess region and the etched insulating layer to form a gate-field electrode layer.Type: ApplicationFiled: July 24, 2012Publication date: March 21, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ho Kyun AHN, Jong-Won Lim, Sung Bum Bae, Sang Choon Ko, Young Rak Park, Woo Jin Chang, Jae Kyoung Mun, Eun Soo Nam, Jeong Jin Kim, Chull Won Ju
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Publication number: 20120092335Abstract: A method and a 3D display apparatus for processing a stereoscopic image signal in high rate by software while using a least number of hardware components in a portable 3D display apparatus based on a mobile Android platform are provided. This method is suitable for a portable terminal apparatus equipped with a kernel layer directly controlling hardware means including a display panel, and an application/middleware layer controlling the kernel layer to display a motion picture through the hardware means. One or more plane image surfaces are first generated from the application/middleware layer and stored in a first frame buffer. An encoded image signal is decoded under the application/middleware layer to restore a YUV image signal representing a stereoscopic image pair. Subsequently, the YUV image signal is converted into an RGB image signal, and left and right images of the RGB image signal are mixed at the kernel layer.Type: ApplicationFiled: October 12, 2011Publication date: April 19, 2012Applicant: 3D NURI CO., LTD.Inventors: Jeong Jin KIM, Chul PARK
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Patent number: 7825523Abstract: A semiconductor package includes a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern, The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region.Type: GrantFiled: December 27, 2006Date of Patent: November 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Publication number: 20100168281Abstract: Disclosed herein are a spalling-preventing composite material composed of fiber and powder, which have different diameters and melting points so as to be capable of realizing the effect of preventing spalling of high-strength concrete and the effect of improving the fluidity of concrete, and a high-strength refractory concrete comprising the spalling-preventing material. The composite material for preventing spalling of high-strength concrete is composed of powder and fiber at 1:1-3, wherein the powder is a polymer powder having a diameter of 0.10-0.5 mm and a melting point of 110-150° C., and the fiber is a conjugate fiber including a first fiber having a diameter of 0.05-0.10 mm, a length of 5-25 mm and a melting point of 150-190° C., and a second fiber having a diameter of 0.01-0.05 mm, a length of 5-25 mm and a melting point of 190-250° C., the first fiber being a polypropylene fiber, and the second fiber being a nylon fiber or a polyvinyl alcohol fiber.Type: ApplicationFiled: December 24, 2009Publication date: July 1, 2010Inventors: Joo Ho Lee, Soon Jeon Park, Jeong Jin Kim, Kwang Ki Kim, Hyung Jae Moon, Yin Seong Hwang, Yong Jeong, Jin Man Choi, Jae Kyung Shin, Se Hoon Kim, Chang Hyoo Choi, Hui Chan Kim
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Patent number: 7576440Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: GrantFiled: November 2, 2006Date of Patent: August 18, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Patent number: 7547977Abstract: In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor substrate; a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.Type: GrantFiled: December 27, 2006Date of Patent: June 16, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Patent number: 7541682Abstract: A semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on at least a part of the peripheral region of the semiconductor substrate. A passivation layer is formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.Type: GrantFiled: November 2, 2006Date of Patent: June 2, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Publication number: 20080288489Abstract: A method for searching patent documents by applying degree of similarity and a system thereof are disclosed. The method for searching patent documents by applying degree of similarity comprises receiving at least one search keyword from a user of the service; searching a document previously stored in a database, by the search keyword; and evaluating a degree of similarity to the search keyword on the document that is searched by the search keyword, wherein the degree of similarity is evaluated by measuring at least one degree among a degree of appearance frequency of the search keyword in the document, a degree of proximity between the search keywords, and a degree of word order between the search keywords. Therefore, patent documents may be searched by arranging the documents according to a degree of similarity to a search keyword, and not according to whether the keyword is included in the patent documents.Type: ApplicationFiled: August 9, 2006Publication date: November 20, 2008Inventor: Jeong-Jin Kim
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Patent number: 7453159Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: GrantFiled: December 27, 2006Date of Patent: November 18, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Patent number: 7419614Abstract: A method of etching and cleaning objects contained in a vessel, includes etching the objects by providing etching solution into the vessel, forcing out the etching solution from the vessel by providing pressurized gas into the vessel; cleaning the objects by providing cleaning solution into the vessel; and draining the cleaning solution from the vessel. By forcing out the etching solution with a pressurized gas such as nitrogen gas, there is no density difference of the etching solution in contact with the objects, leading to uniform etching of the objects.Type: GrantFiled: December 4, 2000Date of Patent: September 2, 2008Assignee: LG Display Co., Ltd.Inventors: Jeong-Jin Kim, Il-Ryong Park, Hae-Joo Choi
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Publication number: 20070108633Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: ApplicationFiled: December 27, 2006Publication date: May 17, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Publication number: 20070108562Abstract: A semiconductor package includes a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern, The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region.Type: ApplicationFiled: December 27, 2006Publication date: May 17, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Hee SONG, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Publication number: 20070108632Abstract: In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor substrate; a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.Type: ApplicationFiled: December 27, 2006Publication date: May 17, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Hee SONG, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Publication number: 20070057383Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: ApplicationFiled: November 2, 2006Publication date: March 15, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hee SONG, Il-Heung CHOI, Jeong-Jin KIM, Hae-Jeong SOHN, Chung-Woo LEE
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Publication number: 20070057367Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: ApplicationFiled: November 2, 2006Publication date: March 15, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hee SONG, Il-Heung CHOI, Jeong-Jin KIM, Hae-Jeong SOHN, Chung-Woo LEE