Abstract: An solder ball mounter includes a stage configured to support a substrate, a ball placer head configured to provide solder balls, and a solder ball mask configured to align the solder balls with the substrate. The solder ball mask includes an upper mask layer including an upper opening having a first diameter, a middle mask layer including a middle opening having a second diameter that is larger than the first diameter, and a lower mask layer.

Abstract: A method may include forming a first grating and a second grating, disposed in a region of vertical overlap of the first and second gratings on different levels, respectively, having substantially the same pitch, and inclined with respect to each other, such that a bias value between the first and second gratings is changed along a length direction of the first and second gratings, using a lithography process. A method may include emitting a beam to the first and second gratings; and obtaining trend information associated with a diffracted beam from an image pattern of a beam from the first and second gratings, using the emitted beam, in which the trend information may concern changes in the intensity of the diffracted beam according to the bias value. An overlay error in at least one grating may be determined based on the trend information and an intensity of a diffracted beam.

Abstract: An apparatus and method for processing a user input in an electronic device are provided. The electronic device includes a touch device detecting a touch input; a pressure device detecting a pressure input; and at least one processor. The at least one processor is configured to if the pressure input is detected, generate an event corresponding to the pressure input, determine if the touch input is detected while the pressure input is detected, if the touch input is detected while the pressure input is detected, update the event to correspond to the pressure input and the touch input, and process the updated event.

Abstract: A method may include forming a first grating and a second grating, disposed in a region of vertical overlap of the first and second gratings on different levels, respectively, having substantially the same pitch, and inclined with respect to each other, such that a bias value between the first and second gratings is changed along a length direction of the first and second gratings, using a lithography process. A method may include emitting a beam to the first and second gratings; and obtaining trend information associated with a diffracted beam from an image pattern of a beam from the first and second gratings, using the emitted beam, in which the trend information may concern changes in the intensity of the diffracted beam according to the bias value. An overlay error in at least one grating may be determined based on the trend information and an intensity of a diffracted beam.

Abstract: A method for measuring wafer alignment is provided. The method includes providing a plurality of first mark patterns extending in a first direction on a wafer, providing at least one second mark pattern on the first mark patterns such that it overlaps and intersects the first mark patterns, irradiating an optical signal onto the first mark patterns and the second mark pattern and obtaining coordinates of the second mark pattern by detecting signals from the second mark pattern.

Abstract: A method of controlling an activation area of a touch screen panel and an electronic device using the same. A method of operating an electronic device, according to an embodiment of the present disclosure, may include: setting a partial area of a touch screen panel, which corresponds to a view window of a cover that is mounted on the electronic device, as an effective touch area when the cover is closed; and when the cover mounted on the electronic device is closed, activating the partial area of the touch screen panel that corresponds to the set effective touch area. In addition, the various embodiments of the present disclosure also include other embodiments as well as the above-described embodiment.

Abstract: A method of detecting an asymmetric portion of an overlay mark includes forming a plurality of virtual overlay marks having a plurality of virtual asymmetric portions. The virtual asymmetric portions may have different sizes with respect to a reference model profile of a reference overlay mark. Virtual information with respect to each virtual overlay mark may be obtained. The virtual information of the virtual overlay marks may be compared with actual information of an actual overlay mark to identify virtual information of the virtual overlay mark corresponding to the actual information of the actual overlay mark. Thus, measuring the overlay of the actual overlay mark may be performed under than the actual asymmetric portion may be excluded from the actual overlay mark, so that the overlay may be accurately measured. As a result, errors may not be generated in a correcting process to a layer using the accurate overlay.

Abstract: Provided are methods of testing pattern reliability and methods of testing a semiconductor device using the same. A method of testing pattern reliability may include acquiring an optical image of a wafer on which a plurality of patterns are formed, evaluating degrees of damage of ones of the plurality of patterns based on the optical image, determining a respective reliability of the ones of the plurality of patterns according to the evaluated respective degrees of damage, and mapping the reliability of the ones of the plurality of patterns based on locations of the respective patterns on the wafer.

Abstract: A method of detecting an asymmetric portion of an overlay mark includes forming a plurality of virtual overlay marks having a plurality of virtual asymmetric portions. The virtual asymmetric portions may have different sizes with respect to a reference model profile of a reference overlay mark. Virtual information with respect to each virtual overlay mark may be obtained. The virtual information of the virtual overlay marks may be compared with actual information of an actual overlay mark to identify virtual information of the virtual overlay mark corresponding to the actual information of the actual overlay mark. Thus, measuring the overlay of the actual overlay mark may be performed under than the actual asymmetric portion may be excluded from the actual overlay mark, so that the overlay may be accurately measured.

Abstract: Provided is a semiconductor package including a high integration semiconductor chip and having a minimum area to be mounted on a circuit board. The semiconductor package includes a semiconductor chip, a plurality of inner leads, and an encapsulant. The plurality of inner leads include upper and bottom surfaces and are electrically connected to the semiconductor chip. The encapsulant covers the semiconductor chip and the plurality of inner leads. The upper surfaces of the plurality of inner leads are fixed to the encapsulant, portions of the bottom surfaces of the plurality of inner leads are exposed from the encapsulant, and the bottom surfaces of the plurality of inner leads are disposed at a different height from a bottom surface of the encapsulant.

Abstract: Provided are highly reliable, high density stacked semiconductor packages including a plurality of semiconductor chips and a method of manufacturing the highly reliable, high density semiconductor package. An embodiment of the stacked semiconductor package includes upper and lower semiconductor packages that are sequentially stacked. The upper and lower semiconductor packages include inner leads connected to semiconductor chips. The lower semiconductor package may further include a plurality of outer leads connected to the inner leads of the lower semiconductor package and that extend outside a encapsulant to be electrically connected to the inner leads of the upper semiconductor package.

Abstract: Provided is a semiconductor package including a high integration semiconductor chip and having a minimum area to be mounted on a circuit board. The semiconductor package includes a semiconductor chip, a plurality of inner leads, and an encapsulant. The plurality of inner leads include upper and bottom surfaces and are electrically connected to the semiconductor chip. The encapsulant covers the semiconductor chip and the plurality of inner leads. The upper surfaces of the plurality of inner leads are fixed to the encapsulant, portions of the bottom surfaces of the plurality of inner leads are exposed from the encapsulant, and the bottom surfaces of the plurality of inner leads are disposed at a different height from a bottom surface of the encapsulant.

Abstract: A wideband multi-tone transceiver system interoperable with Asymmetric Digital Subscriber Line (ADSL) transceiver system, and including a two-step transceiver system having a discrete multi-tone transceiver system and a cosine modulated filter bank (CMFB) transmultiplexer. The two-step transceiver system provides a physically transparent transmission channel to each sub-band signal by minimizing the interference between sub-bands regardless of the transmission channel characteristics. The two-step transceiver system is realized with a comparably simple structure, and the circuit size is drastically reduced by sharing the FFT function with other sub-channels with the maximal utilization of the high-speed circuit when realizing each sub-channel's DMT modulation and demodulation function.

Abstract: Method for designing TEQs(Time-domain Equalizers) for different signal bands in a VDSL transmission system, including the steps of dividing an entire signal band into at least two signal bands, and respectively modulating the divided signal bands before transmission at a transmitter, and applying respective transmitted signal bands to an algorithm that can reduce channel response lengths of the respective signal bands at a receiver, for obtaining respective TEQs, and connecting the TEQs in series, wherein an entire signal band is divided into a low frequency signal band and a high frequency signal band, with the low frequency signal band allocated smaller than the high frequency signal band, and preferably the low frequency signal band includes the signal band used in an ADSL, whereby reducing an amount of hardware and assuring an interchangeability with the ADSL transmission system.

Abstract: A finite impulse response (FIR) filter for wave-shaping digital quadrature amplitude modulation (QAM) symbols is disclosed, in which multipliers are replaced with multiplexers, the replaced multiplexers are utilized to receive the symbols directly from a symbol encoder without zero (0) interpolations, and the critical path is reduced by shifting the position of a delay device. The filter includes a first FIR means for delaying the externally inputted symbol data, and for utilizing the delayed symbol data as selection signals to sum up the selected multiplication product (selected from among products obtained by multiplying the symbol values by a pre-set filter tab coefficient) and the selected value selected by a first multiplexing means. A second FIR means delays again the delayed symbol data of the first FIR means, and utilizes the delayed symbol data as selection signals to sum up the selected multiplication product and the output value of the first FIR means.

Abstract: The present invention relates to a fixed length packet switching apparatus using multiplexers and demultiplexers in which the apparatus has an output buffer-type construction, protects itself from a temporary overflow occurrence of an output terminal and has the construction of the mutual flow control to enhance its entire performance. The present invention can protect the entire operations as well as enhance the entire performance of the switching apparatus by preventing an obstacle of the switching apparatus due to an overflow temporarily generated from an output terminal, process without a loss of excessive cells a traffic phenomenon of one output port in the switching apparatus, reduce the necessary buffer according to the effect of the rate gain and process smoothly input traffic of the internal buffer having a burst characteristic.