Patents by Inventor Jeong-kyu Ha
Jeong-kyu Ha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079311Abstract: A semiconductor package includes a film substrate; a wiring layer provided on the film substrate; and a semiconductor chip provided on the wiring layer and electrically connected to the wiring layer. The film substrate includes a first layer, wherein the first layer is an insulating layer having the wiring layer thereon. The film substrate further includes a second layer, wherein the second layer is attached to a bottom of the first layer and comprises a gas. The second layer is configured to be peeled off of the first layer.Type: ApplicationFiled: August 1, 2023Publication date: March 7, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Hyun CHO, Jeong-Kyu Ha, Jae-Min Jung
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Publication number: 20240079312Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: KwanJai LEE, Jae-Min JUNG, Jeong-Kyu HA, Sang-Uk HAN
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Patent number: 11830803Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.Type: GrantFiled: March 21, 2022Date of Patent: November 28, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Kwanjai Lee, Jae-Min Jung, Jeong-Kyu Ha, Sang-Uk Han
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Patent number: 11764140Abstract: A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.Type: GrantFiled: August 2, 2021Date of Patent: September 19, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Uk Han, Duck Gyu Kim, Min Ki Kim, Jae-Min Jung, Jeong-Kyu Ha
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Publication number: 20230176108Abstract: A semiconductor package includes a base film having a first mount section, a first folding section, a second folding section, and a second mount section. A first semiconductor chip is disposed on the first mount section of the base film. A second semiconductor chip is disposed on the second mount section of the base film. Test pads are disposed on the first or second folding sections of the base film and is connected to each of the first and second semiconductor chips. Connection pads are disposed on the first or second mount sections of the base film and are connected to each of the first and second semiconductor chips. The first and second folding sections vertically overlap each other. The test pads are interposed between and buried by the first and second folding sections.Type: ApplicationFiled: August 1, 2022Publication date: June 8, 2023Inventors: SEUNGHYUN CHO, KWANJAI LEE, JAE-MIN JUNG, JEONG-KYU HA, SANG-UK HAN
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Patent number: 11600556Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, a first chip pad on a bottom surface of the semiconductor chip and adjacent to a first lateral surface in a first direction of the semiconductor chip, the first lateral surface separated from the first chip pad from a plan view in a first direction, and a first lead frame coupled to the first chip pad. The first lead frame includes a first segment on a bottom surface of the first chip pad and extending from the first chip pad in a second direction opposite to the first direction and away from the first lateral surface of the semiconductor chip, and a second segment which connects to a first end of the first segment and then extends along the first direction to extend beyond the first lateral surface of the semiconductor chip after passing one side of the first chip pad, when viewed in the plan view.Type: GrantFiled: April 14, 2021Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Minki Kim, Duckgyu Kim, Jae-Min Jung, Jeong-Kyu Ha, Sang-Uk Han
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Publication number: 20230037785Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.Type: ApplicationFiled: March 21, 2022Publication date: February 9, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: KwanJai LEE, Jae-Min JUNG, Jeong-Kyu HA, Sang-Uk HAN
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Publication number: 20220165652Abstract: A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.Type: ApplicationFiled: August 2, 2021Publication date: May 26, 2022Inventors: Sang-Uk HAN, Duck Gyu KIM, Min Ki KIM, Jae-Min JUNG, Jeong-Kyu HA
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Publication number: 20220068771Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, a first chip pad on a bottom surface of the semiconductor chip and adjacent to a first lateral surface in a first direction of the semiconductor chip, the first lateral surface separated from the first chip pad from a plan view in a first direction, and a first lead frame coupled to the first chip pad. The first lead frame includes a first segment on a bottom surface of the first chip pad and extending from the first chip pad in a second direction opposite to the first direction and away from the first lateral surface of the semiconductor chip, and a second segment which connects to a first end of the first segment and then extends along the first direction to extend beyond the first lateral surface of the semiconductor chip after passing one side of the first chip pad, when viewed in the plan view.Type: ApplicationFiled: April 14, 2021Publication date: March 3, 2022Inventors: MINKI KIM, DUCKGYU KIM, JAE-MIN JUNG, JEONG-KYU HA, SANG-UK HAN
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Publication number: 20200372232Abstract: Disclosed are fingerprint sensor packages and display apparatuses including the same. The fingerprint sensor package comprises a flexible film having a top surface and a bottom surface opposite to the top surface, a fingerprint sensor surrounded by a cap, and a display driver integrated circuit on the flexible film. The fingerprint sensor and the display driver integrated circuit are mounted on the top surface of the flexible film.Type: ApplicationFiled: August 11, 2020Publication date: November 26, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: WOONBAE KIM, Jikho SONG, Sungeun JO, Ji-Yong PARK, Jeong-Kyu HA
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Patent number: 10776601Abstract: Disclosed are fingerprint sensor packages and display apparatuses including the same. The fingerprint sensor package comprises a flexible film having a top surface and a bottom surface opposite to the top surface, a fingerprint sensor surrounded by a cap, and a display driver integrated circuit on the flexible film. The fingerprint sensor and the display driver integrated circuit are mounted on the top surface of the flexible film.Type: GrantFiled: July 5, 2018Date of Patent: September 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woonbae Kim, Jikho Song, Sungeun Jo, Ji-Yong Park, Jeong-Kyu Ha
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Patent number: 10504829Abstract: A semiconductor package includes a substrate having a top surface on which a semiconductor chip is mounted and a bottom surface opposite the top surface, an upper metal pattern including an upper connection region to which an external electrical device is connected and a chip connection region to which the semiconductor chip is connected, a lower metal pattern including a lower connection region to which other external electrical device is connected, and an intermediate metal pattern electrically connecting the upper and lower metal patterns. The upper metal pattern provides at least three groups of inner leads. The lower metal pattern provides at least three groups of outer leads. A module, such as that of a display device, may include the semiconductor package.Type: GrantFiled: August 7, 2018Date of Patent: December 10, 2019Assignee: Samsung Electronics Co., Ltd.Inventor: Jeong-Kyu Ha
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Publication number: 20190213373Abstract: Disclosed are fingerprint sensor packages and display apparatuses including the same. The fingerprint sensor package comprises a flexible film having a top surface and a bottom surface opposite to the top surface, a fingerprint sensor surrounded by a cap, and a display driver integrated circuit on the flexible film. The fingerprint sensor and the display driver integrated circuit are mounted on the top surface of the flexible film.Type: ApplicationFiled: July 5, 2018Publication date: July 11, 2019Inventors: Woonbae KIM, Jikho SONG, Sungeun JO, Ji-Yong PARK, Jeong-Kyu HA
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Publication number: 20190189551Abstract: A semiconductor package includes a substrate having a top surface on which a semiconductor chip is mounted and a bottom surface opposite the top surface, an upper metal pattern including an upper connection region to which an external electrical device is connected and a chip connection region to which the semiconductor chip is connected, a lower metal pattern including a lower connection region to which other external electrical device is connected, and an intermediate metal pattern electrically connecting the upper and lower metal patterns. The upper metal pattern provides at least three groups of inner leads. The lower metal pattern provides at least three groups of outer leads. A module, such as that of a display device, may include the semiconductor package.Type: ApplicationFiled: August 7, 2018Publication date: June 20, 2019Inventor: JEONG-KYU HA
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Patent number: 10304764Abstract: In an embodiment, the film product includes a film substrate having a first surface and a second surface opposite the first surface. The film substrate has a length in a first direction and a width in a second direction perpendicular to the first direction. A first plurality of pads is on one of the first surface and the second surface, and the first plurality of pads is arranged in a third direction, the third direction being diagonal with respect to at least one of the first direction and the second direction. At least one merge line is electrically connecting at least two of the first plurality of pads.Type: GrantFiled: March 21, 2017Date of Patent: May 28, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Yechung Chung, Woonbae Kim, Soyoung Lim, Jeong-Kyu Ha
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Patent number: 10282587Abstract: A sensing module substrate and a sensing module including the same are provided. The sensing module substrate includes a film substrate having a first surface and a second surface; sensing vias which penetrate the film substrate from the first surface to the second surface, each of the sensing vias being configured to be coupled to pixels of a semiconductor chip; and an interconnection pattern provided on at least one of the first surface and the second surface of the film substrate.Type: GrantFiled: December 30, 2016Date of Patent: May 7, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Inho Choi, Youngdoo Jung, Woonbae Kim, Jungwoo Kim, Ji-Yong Park, Kyoungsuk Yang, Jeong-Kyu Ha
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Patent number: 10134667Abstract: Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF semiconductor package includes a film substrate, a conductive interconnection located on at least one surface of the film substrate and an output pin connected to the conductive interconnection and located at one edge on a first surface of the film substrate, a semiconductor chip connected to the conductive interconnection and mounted on the first surface of the film substrate, a solder resist layer on the first surface of the film substrate to cover at least a portion of the conductive interconnection, and at least one barrier dam on the solder resist layer between the semiconductor chip and the output pin.Type: GrantFiled: April 27, 2018Date of Patent: November 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-woo Kim, Jae-min Jung, Ji-yong Park, Jeong-kyu Ha, Woon-bae Kim
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Publication number: 20180247882Abstract: Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF semiconductor package includes a film substrate, a conductive interconnection located on at least one surface of the film substrate and an output pin connected to the conductive interconnection and located at one edge on a first surface of the film substrate, a semiconductor chip connected to the conductive interconnection and mounted on the first surface of the film substrate, a solder resist layer on the first surface of the film substrate to cover at least a portion of the conductive interconnection, and at least one barrier dam on the solder resist layer between the semiconductor chip and the output pin.Type: ApplicationFiled: April 27, 2018Publication date: August 30, 2018Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-woo Kim, Jae-min Jung, Ji-yong Park, Jeong-kyu Ha, Woon-bae Kim
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Patent number: 9978674Abstract: Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF semiconductor package includes a film substrate, a conductive interconnection located on at least one surface of the film substrate and an output pin connected to the conductive interconnection and located at one edge on a first surface of the film substrate, a semiconductor chip connected to the conductive interconnection and mounted on the first surface of the film substrate, a solder resist layer on the first surface of the film substrate to cover at least a portion of the conductive interconnection, and at least one barrier dam on the solder resist layer between the semiconductor chip and the output pin.Type: GrantFiled: April 5, 2017Date of Patent: May 22, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-woo Kim, Jae-min Jung, Ji-yong Park, Jeong-kyu Ha, Woon-bae Kim
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Patent number: 9929083Abstract: A semiconductor package includes a flexible film substrate including a chip mounting region and a cut-line interposed between an inner region and an outer region of the flexible film substrate, the cut-line partially surrounding the inner region. The semiconductor package further includes first interconnection lines extending in the inner region from a first side of the chip mounting region towards an edge of the inner region of the flexible film substrate, and second interconnection lines extending in the outer region from a second side of the chip mounting region towards an edge of the outer region of the flexible film substrate. The edge of the inner region and the edge of the outer region are located on the first side of the semiconductor chip.Type: GrantFiled: January 22, 2016Date of Patent: March 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventor: Jeong-Kyu Ha