Abstract: Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

Abstract: Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern.

Abstract: A phase edge phase shift mask and a fabrication method thereof for enforcing a width of a field gate image located on a field region, which is weakened by a two exposure process, by using a phase shift mask and a trim mask on a semiconductor substrate, and enforcing a width of the field gate image to maximize a current driving capability of the semiconductor device.

Abstract: The apparatus for cleaning a wafer includes an energy concentration relieving member positioned at the side of the wafer. An elongated portion of a probe extends over and substantially parallel to the wafer surface. A vibrator is attached to a rear end of the probe for vibrating the probe such that the elongated portion transfers acoustic vibrational energy to the wafer and dislodges debris.

Abstract: A megasonic cleaning apparatus is provided for removing contamination particles on a wafer. The megasonic cleaning apparatus includes a piezoelectric transducer and an energy transfer rod. The piezoelectric transducer is for generating megasonic energy. The energy transfer rod installed over the wafer along a radial direction of the wafer is for distributing the megasonic energy to cleaning solution over the wafer and for vibrating the cleaning solution. The energy transfer rod is shaped and sized to uniformly distribute energy in the radial direction of the wafer through the cleaning solution to remove the contamination particles from the wafer.

Abstract: Embodiments of the invention include a megasonic energy cleaning apparatus that has the ability to rotate the wafer to be cleaned, as well as rotate the cleaning probe during the cleaning process. Rotating the cleaning probe while the wafer is being cleaned is effective to increase the cleaning action of the apparatus while also minimizing damage to the wafer. Curved grooves, such as a spiral groove, can be etched into the cleaning probe to minimize forming harmful waves that could potentially cause damage to the wafer surface or to structures already made on the surface. Using a cleaning probe having a curved groove while also rotating the cleaning probe effectively cleans particles from a wafer while also limiting damage to the surface of the wafer.

Abstract: A photoresist composition may include formulas 1 and 2: ?where R is an acetal group or a ter-butyloxy carbonyl (t-BOC) group, n and m are integers, n/(m+n) is 0.01?0.8, and m/(m+n) is 1?[n/(m+n)], ?where r is an integer between 8-40. A method for forming photoresist patterns may include forming a photoresist layer on a semiconductor substrate and exposing and developing the photoresist layer using a mask pattern that includes first areas having a light transmissivity of about 100% and second areas having a light transmissivity of between about 10% and about 30%.

Abstract: A phase edge phase shift mask and a fabrication method thereof for enforcing a width of a field gate image located on a field region, which is weakened by a two exposure process, by using a phase shift mask and a trim mask on a semiconductor substrate, and enforcing a width of the field gate image to maximize a current driving capability of the semiconductor device.

Abstract: Disclosed is a method of planarizing a non-volatile memory device. After forming a floating gate structure on a cell area of a semiconductor substrate, a conductive layer, a hard mask layer and a first insulating layer are sequentially formed on the entire surface of the resultant structure. After removing the first insulating layer of the cell area to leave a first insulating layer pattern only on the peripheral circuit area, the hard mask layer of the cell area is removed. A second insulating layer is formed on the conductive layer and the insulating layer pattern to increase the height of the insulating layer on the peripheral circuit area. The second insulating layer and the first insulating layer pattern are removed until the floating gate structure is exposed, thereby planarizing the cell area and the peripheral circuit area.

Abstract: Embodiments of the invention include a megasonic energy cleaning apparatus that has the ability to rotate the wafer to be cleaned, as well as rotate the cleaning probe during the cleaning process. Rotating the cleaning probe while the wafer is being cleaned is effective to increase the cleaning action of the apparatus while also minimizing damage to the wafer. Curved grooves, such as a spiral groove, can be etched into the cleaning probe to minimize forming harmful waves that could potentially cause damage to the wafer surface or to structures already made on the surface. Using a cleaning probe having a curved groove while also rotating the cleaning probe effectively cleans particles from a wafer while also limiting damage to the surface of the wafer.

Abstract: The apparatus for cleaning a wafer includes an energy concentration relieving member positioned at the side of the wafer. An elongated portion of a probe extends over and substantially parallel to the wafer surface. A vibrator is attached to a rear end of the probe for vibrating the probe such that the elongated portion transfers acoustic vibrational energy to the wafer and dislodges debris.

Abstract: A megasonic cleaning apparatus is provided for removing contamination particles on a wafer. The megasonic cleaning apparatus includes a piezoelectric transducer and an energy transfer rod. The piezoelectric transducer is for generating megasonic energy. The energy transfer rod installed over the wafer along a radial direction of the wafer is for distributing the megasonic energy to cleaning solution over the wafer and for vibrating the cleaning solution. The energy transfer rod is shaped and sized to uniformly distribute energy in the radial direction of the wafer through the cleaning solution to remove the contamination particles from the wafer.

Abstract: A photoresist composition may include formulas 1 and 2: 1

Abstract: Disclosed is a method of planarizing a non-volatile memory device. After forming a floating gate structure on a cell area of a semiconductor substrate, a conductive layer, a hard mask layer and a first insulating layer are sequentially formed on the entire surface of the resultant structure. After removing the first insulating layer of the cell area to leave a first insulating layer pattern only on the peripheral circuit area, the hard mask layer of the cell area is removed. A second insulating layer is formed on the conductive layer and the insulating layer pattern to increase the height of the insulating layer on the peripheral circuit area. The second insulating layer and the first insulating layer pattern are removed until the floating gate structure is exposed, thereby planarizing the cell area and the peripheral circuit area.

Abstract: A method of forming a contact hole for a dual damascene interconnection of a semiconductor device includes forming a first photoresist layer pattern on an insulating layer of a semiconductor substrate, the first photoresist layer pattern having a first opening with a first width. A groove having the first width to a prescribed depth of the insulating layer is formed by performing an etching process using the first photoresist layer pattern as an etch mask. A second photoresist layer pattern on the insulating layer having the groove therein is formed. The second photoresist layer has a second opening with a second width, wherein the second width is substantially equal to or larger than the first width of the groove. A contact hole exposing the semiconductor substrate is formed by performing an etching process using the second photoresist layer pattern as an etch mask.

Abstract: A photo process system for semiconductor wafers prevents air from flowing across the top of a baking region to produce a stable downward laminar air flow in front of baking units disposed at several levels in the baking region. The baking region is located on one side of a housing, and a coating unit for coating a wafer with a photoresist is located on the other side of the housing. The housing has a clean air entrance and air filters at an upper portion thereof, and a clean air discharge opening at the very bottom thereof. An air flow containment dam prevents clean air entering the housing from flowing horizontally at the top of the baking region. Such a horizontal flow of air would otherwise produce turbulence severely affecting the ability of the air to flow downward across the front of the baking units and toward the discharge opening as a laminar air flow. The laminar air flow hardly passes into the baking units and thus, hardly induces temperature variations in the coated wafers that are being baked.