Abstract: A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.

Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

Abstract: A half voltage generator includes input buffer unit that receives an input voltage and outputs control voltage and a reference voltage using a power supply voltage, and a voltage division unit that divides the power supply voltage in half and outputs the half power supply voltage in response the control voltage and reference voltage. A current mirror receives the reference voltage unit and current limits the operation of an output buffer unit, which is controlled by an output voltage of the voltage division unit to output the half power supply voltage. A push-pull driving unit is controlled by the output voltage of the output buffer unit to output the half power supply voltage, which has an improved current driving capacity, as a final output voltage.

Abstract: A half voltage generator includes input buffer unit that receives an input voltage and outputs control voltage and a reference voltage using a power supply voltage, and a voltage division unit that divides the power supply voltage in half and outputs the half power supply voltage in response the control voltage and reference voltage. A current mirror receives the reference voltage unit and current limits the operation of an output buffer unit, which is controlled by an output voltage of the voltage division unit to output the half power supply voltage. A push-pull driving unit is controlled by the output voltage of the output buffer unit to output the half power supply voltage, which has an improved current driving capacity, as a final output voltage.