Abstract: A semiconductor device structure, including integrated circuits of semiconductor chips and scribe lanes between the regions in which the circuits have been formed, has at least one redistribution pad disposed in one of the scribe lanes for simultaneously testing a group of the integrated circuits, and a metal interconnection structure disposed beneath the redistribution pad(s). The metal interconnection structure includes at least conductive via contacting the redistribution pad at the bottom of the pad. The conductive via(s) is/are arranged so that at least a portion of each via remains attached to the redistribution pad when the structure is sawed along the scribe lane.

Abstract: A semiconductor device structure, including integrated circuits of semiconductor chips and scribe lanes between the regions in which the circuits have been formed, has at least one redistribution pad disposed in one of the scribe lanes for simultaneously testing a group of the integrated circuits, and a metal interconnection structure disposed beneath the redistribution pad(s). The metal interconnection structure includes at least conductive via contacting the redistribution pad at the bottom of the pad. The conductive via(s) is/are arranged so that at least a portion of each via remains attached to the redistribution pad when the structure is sawed along the scribe lane.

Abstract: A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.

Abstract: A voltage boosting circuit includes a first voltage boosting circuit configured to receive an external power supply voltage, and pump the external power supply voltage to a second boosting voltage higher than the external supply voltage in a single pumping stage, and a second voltage boosting circuit configured to receive the second boosting voltage and pump the second boosting voltage to a first boosting voltage higher than the second boosting voltage in two pumping stages.

Abstract: A voltage boosting circuit includes a first voltage boosting circuit configured to receive an external power supply voltage, and pump the external power supply voltage to a second boosting voltage higher than the external supply voltage in a single pumping stage, and a second voltage boosting circuit configured to receive the second boosting voltage and pump the second boosting voltage to a first boosting voltage higher than the second boosting voltage in two pumping stages.

Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

Abstract: A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.

Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

Abstract: A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.

Abstract: A digital temperature detection circuit adapted for use with a semiconductor device is disclosed. The digital temperature detection circuit comprises a digital temperature generation unit adapted to detect an internal temperature of the semiconductor device, convert the internal temperature into perception data in accordance with a perception data code, and output the perception data. The digital temperature detection circuit further comprises an offset shift unit adapted to shift the perception data in accordance with offset data to thereby generate standard data; and, an offset generation unit adapted to generate the offset data, wherein the offset generation unit is controlled from outside of the digital temperature detection circuit.

Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

Abstract: A digital temperature detection circuit for a semiconductor circuit comprises a digital temperature defection block and a data conversion block. The digital temperature detection block is adapted to detect an internal temperature of the semiconductor device and generate detection data having a data value that varies according to the detected internal temperature. The data conversion block is adapted to convert the detection data into standard data with a predetermined response interval using first and second sample data having respective data values that are determined by input from an external source.

Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

Abstract: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

Abstract: A digital temperature detection circuit adapted for use with a semiconductor device is disclosed. The digital temperature detection circuit comprises a digital temperature generation unit adapted to detect an internal temperature of the semiconductor device, convert the internal temperature into perception data in accordance with a perception data code, and output the perception data. The digital temperature detection circuit further comprises an offset shift unit adapted to shift the perception data in accordance with offset data to thereby generate standard data; and, an offset generation unit adapted to generate the offset data, wherein the offset generation unit is controlled from outside of the digital temperature detection circuit.

Abstract: A digital temperature detection circuit for a semiconductor circuit comprises a digital temperature defection block and a data conversion block. The digital temperature detection block is adapted to detect an internal temperature of the semiconductor device and generate detection data having a data value that varies according to the detected internal temperature. The data conversion block is adapted to convert the detection data into standard data with a predetermined response interval using first and second sample data having respective data values that are determined by input from an external source.